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Power On Reset (POR)

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

6.2

Power On Reset (POR)

Power On Reset is the reset initiated when the device is being powered up. It is generated by the Voltage

Regulator when the voltage supply of the device is below a certain threshold (called the POR trip point).

The POR is used to reset or control the following:

•

Flash internal circuits

•

CRG system reset generation logic

•

CRG debug reset generation logic

•

Pad/Level shifter inhibitors

6.3

System Reset

The System Reset is the main reset in the system that is used to reset the majority of the logic in the system.

It can be caused by any of the following events:

All of the above sources may be detected by software (after the reset) by reading the appropriate register(s)

in the CRG module. Note that the use of the MRSR register in the MCM is deprecated.

6.4

Debug Reset

The Debug Reset is generated from the Power-On Reset (POR) of the system, and is intended to reset the

debug logic, which should not be reset during a general system reset (i.e.-when the user presses a reset

button).

On the MAC72xx, the Debug Reset is initiated by either of the following two conditions:

•

a Power-On Reset (POR)

•

Setting of bit 5 in the SC4 Test Register (See Section 35.1.1, “JTAG Test Register (SC4)”)

Asserting the debug reset will reset the following logic on the MAC72xx:

•

EICE in the ARM7 core, including the TAP state machine

•

JTAG synchronization logic in the Test Controller

•

SC4 register in the Test Controller

Table 6-1. System Reset Sources

Event

Source

Maskable ?

Power On Reset (POR)

Voltage Regulator

Low Voltage Reset (LVR)

Voltage Regulator

RESET

External

Software Watchdog Timer (SWT)

MCM

Yes (In the MCM)

Crystal Monitor Reset

Crystal Monitor

Yes (In the CRG)

Software Reset

SSM

Yes

Illegal Address

Not implemented

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