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Software Reset

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

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SC5 register in the Test Controller

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SC6 register in the Test Controller

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SC7 register in the Test Controller

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BIST muxing in the Test Controller

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Scan testpoints in the Test Controller

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The debug reset assertion logic in the Test Controller (i.e.-self clearing reset)

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Nexus registers

What is not explicitly reset are the Nexus registers, which are reset solely by taking the ARM7 TAP state

machine into the Test-Logic Reset State ($F). Since the ARM7 core TAP state machine is driven by the

debug reset, and resets into the Test-Logic Reset State, this effectively forces the reset of the Nexus

registers as well.

6.5

Software Reset

A software initiated reset of the system may be performed by performing a series of writes to the Software

Reset register in the SSM module. Please refer to Chapter 25, “System Service Module

(SSM_MAC7202)” for details on this. Performing a software reset in this manner is virtually identical to

resetting the device via the RESET pin.

6.6

Reset Implementation

Figure 6-1 illustrates the resets in the MAC72xx. Some points to note are:

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The Nexus is reset by cycling the TAP controller in the A7 through the Test-Logic Reset state ($F).

This is done inside the Nexus block.

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Since the Debug Reset is asserted during a Power On Reset, and the TAP State Machine is reset to

the Test-Logic Reset state on a Debug Reset, the Nexus logic will automatically be reset on a POR

event without the need to explicitly use the POR signal in the Nexus.

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Bringing up the MAC72xx in debug mode will consist of the following steps:

— Power on the MAC72xx. This will reset the ARM7 core, EICE and Nexus.

— A breakpoint at address $0000 0000 is programmed into the EICE

— The external reset is asserted, resetting the system except for the EICE and Nexus

— The processor boots, and fetches its first instruction from $0000 00000, which hits the

previously hit breakpoint, and the system enters DEBUG mode.

Alternatively, the following series of steps may also be used:

— Power on the MAC72xx, while holding the RESET pin low (asserted). This will reset the EICE

and Nexus, but hold the core in a reset state

— A breakpoint at address $0000 0000 is programmed into the EICE

— The external reset is released, starting the execution of the core

— The processor boots, and fetches its first instruction from $0000 00000, which hits the

previously hit breakpoint, and the system enters DEBUG mode.

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Switching Nexus ports will consist of the following steps:

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