PAC7202MPV70 datasheet(67/976 Pages) FREESCALE

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Terminology

MAC7200 Microcontroller Family Reference Manual, Rev. 2

Freescale Semiconductor

lxvii

Table ii. Terminology

Terms

Description

Active Message

Buffer

A Message Buffer is said to be “active” if it can participate in the current matching or arbitration

process. An Rx MB with a ‘0000’ code is inactive. Similarly, a Tx MB with a ‘1000’ code is also

inactive. An MB is temporarily deactivated when the CPU writes to the C/S field (see

Section 28.2.7.6.1, “Message Buffer Deactivation).”

ADB

Allowable disconnect boundary

ADC

Analog to Digital converter: A module to convert analog signals into digital (binary) values

AIPS

AMBA™ to IPS interface unit

ALC

Amplitude Limitation Control

ATD

Analog-to-digital (converter). Frequently used synonymously with ADC

ATM

Asynchronous transfer mode

ATMU

Address translation and mapping unit

Auxiliary Port

Refers to Nexus auxiliary port. Used as auxiliary port to the IEEE 1149.1 JTAG interface.

Baud Rate

Rate of data transmission in bits per second.

Buffer descriptor

BDM

Background Debug Module

BIU

Bus Interface Unit, contains all system level customization required to make the H7Fb module

part of an SoC.

Branch Trace

Messaging (BTM)

Visibility of addresses for taken branches and exceptions, and the number of sequential

instructions executed between each taken branch.

Breakpoint

Processor is halted when all previous instructions are retired and just prior to any architectural

state change by the instruction associated with a pre-selected address.

CAN

Controller Area Network, a serial communication protocol.

CFM

Common Flash Module. Acronym used throughout this document to reference the Flash

memory module. The CFM includes the Common Flash bus interface, IP bus interface, Flash

command controller, Flash memory controller, and Flash arrays.

Clock Phase

Determines when the data should be sampled relative to the active edge of SCK

Clock Polarity

Determines the idle state of the SCK signal.

Clock Monitor

coherency / coherent

access

Coherent access is used to indicate an action to guarantee data consistency, preventing data

from being accessed simultaneously using different methods in such a way that it is not

completely updated before being used.

Command Write

Sequence

A three-stop command instruction sequence to program, erase, or verify the Flash memory.

Clock Prescaler

CPI

CAN Protocol Interface, a FlexCAN sub-module containing the CAN protocol engine.

CPU

Central Processor Unit

CRC

Cyclic Redundancy Check.

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