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AT91SAM7SE512 Datasheet(PDF) 40 Page - ATMEL Corporation |
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AT91SAM7SE512 Datasheet(HTML) 40 Page - ATMEL Corporation |
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40 / 47 page ![]() 40 6222ES–ATARM–15-Dec-09 AT91SAM7SE512/256/32 Preliminary – 8- to 16-bit programmable data length per chip select – Programmable phase and polarity per chip select – Programmable transfer delays per chip select, between consecutive transfers and between clock and data – Programmable delay between consecutive transfers – Selectable mode fault detection – Maximum frequency at up to Master Clock 10.8 Two Wire Interface • Master, Multi-Master and Slave Mode Operation • Compatibility with standard two-wire serial memories • One, two or three bytes for slave address • Sequential read/write operations • Bit Rate: Up to 400 Kbit/s • General Call Supported in Slave Mode 10.9 USART • Programmable Baud Rate Generator • 5- to 9-bit full-duplex synchronous or asynchronous serial communications – 1, 1.5 or 2 stop bits in Asynchronous Mode – 1 or 2 stop bits in Synchronous Mode – Parity generation and error detection – Framing error detection, overrun error detection – MSB or LSB first – Optional break generation and detection – By 8 or by 16 over-sampling receiver frequency – Hardware handshaking RTS - CTS – Modem Signals Management DTR-DSR-DCD-RI on USART1 – Receiver time-out and transmitter timeguard – Multi-drop Mode with address generation and detection • RS485 with driver control signal • ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards – NACK handling, error counter with repetition and iteration limit •IrDA ® modulation and demodulation – Communication at up to 115.2 Kbps • Test Modes – Remote Loopback, Local Loopback, Automatic Echo 10.10 Serial Synchronous Controller • Provides serial synchronous communication links used in audio and telecom applications • Contains an independent receiver and transmitter and a common clock divider |
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