BQ76PL536PAP datasheet(13/58 Pages) TI

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bq76PL536

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SLUSA08A – DECEMBER 2009 – REVISED JULY 2010

Vertical Communications Bus (continued)

Typical values stated where TA = 25ºC and BAT = 20 V, Min/Max values stated where TA = –40˚C to 85ºC and BAT = 7.2 V to

27 V

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

tLS_DELAY

SCLK_S to SCLK_N, CS_S to

CS_N, SDI_S to SDI_N, SDO_N to

SDO_S delay time

ANALOG-TO-DIGITAL CONVERSION (ADC)

General Features

The integrated 14-bit (unsigned) high-speed successive approximation register (SAR) analog-to-digital converter

uses an integrated band-gap reference voltage (VREF) for the cell and brick measurements. The ADC has a

front-end multiplexer for nine inputs – six cells, two temperature sensors, and one general-purpose analog input

(GPAI). The GPAI input can further be multiplexed to measure the brick voltage between the BATx pin and VC0

or the voltage between the GPAI+ and GPAI– pins.

The ADC and reference are factory trimmed to compensate for gain, offset, and temperature-induced errors for

all inputs. The measurement result is not allowed to roll over due to offset error at the top and bottom of the

range, i.e., a reading near zero does not underflow to 0x03ff due to offset error, and vice-versa.

The converter returns 14 valid unsigned magnitude bits in the following format:

<00xxxxxx xxxxxxxx>

Each word is returned in big-endian format in a register pair consisting of two adjacent 8-bit registers. The MSB

of the word is located in the lower-address register of the pair, i.e., data for cell 1 is returned in registers 0x03

and 0x04 as 00xxxxxx xxxxxxxxb.

Designer Note: The signal used to drive the ADC inputs sees about 45 pF of input capacitance when the

mux switches the input to the ADC. The signal source should be capable of driving this capacitance without

introducing error. The sampling time of the ADC is approximately 1 ms when the default 3-ms conversion time

is selected. Therefore, the signal source must be capable of charging the 45-pF capacitance in

approximately 200 nS to allow 5 t for settling; otherwise, the obtained reading will be in error.

Designer Note: The accuracy of the part may be affected by soldering, and may depend on the soldering

process used. This has been typically measured at less than ±2 mV (IC typically reads higher than actual) at

3.6 V/cell input. The offset is fixed, and permanent after soldering. The effect is introduced in the ADC after

the multiplexer, and therefore affects all inputs in the same way. The effect is per input, and not cumulative

for all inputs. This error is in addition to the accuracy specification in the data sheet.

3 to 6 Series Cell Configuration

When fewer than 6 cells are used, the most-positive cell voltage of the series string should be connected to the

BAT1/BAT2 pins, through the RC input network shown in the Reference Schematic section. Unused VCx inputs

should be connected to the next VCx input down until an input connected to a cell is reached – i.e., in a four cell

stack, VC6 connects to VC5, which connects to VC4.

The internal multiplexer control can be set to scan only inputs which are connected to cells, thereby speeding up

conversions slightly. The multiplexer is controlled by the ADC_CONTROL[CN2:0] bits.

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