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DAC5682Z Datasheet(PDF) 18 Page - Texas Instruments |
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DAC5682Z Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 59 page ![]() TEST METHODOLOGY DAC-A DAC-B 100 100 100 100 opt. PLL Loop Filter DLL DAC5682ZDAC CDCM7005 DCLK SYNC D0 D15 Agilent 81205A ParBERT Pattern Memory 100 Opt. Clock Divider DAC5682ZEVM DAC5682ZEVMSMAAdapterBoard 100 100 100 100 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V Agilent 8133A PulseGenerator Optional Divider HP8665B Synthesized Signal Generator P N P N P N P N Rohde & Schwartz FSU Spectrum Analyzer 36 each SMA-SMAcables SwapCable ForDAC-B measurements DEFINITION OF SPECIFICATIONS DAC5682Z SLLS853C – AUGUST 2007 – REVISED JUNE 2009 ........................................................................................................................................................ www.ti.com Typical AC specifications were characterized with the DAC5682ZEVM using the test configuration shown in Figure 25. A sinusoidal master clock frequency is generated by an HP8665B signal generator and into a splitter. One output drives an Agilent 8133A pulse generator, and the other drives the CDCM7005 clock driver. The 8133A converts the sinusoidal frequency into a square wave output clock and drives an Agilent ParBERT 81250A pattern-generator clock. On the EVM, the DAC5682Z CLKIN/C input clock is driven by an CDCM7005 clock distribution chip that is configured to simply buffer the external 8665B clock or divide it down for PLL test configurations. The DAC5682Z output is characterized with a Rohde and Schwarz FSU spectrum analyzer. For WCDMA signal characterization, it is important to use a spectrum analyzer with high IP3 and noise subtraction capability so that the spectrum analyzer does not limit the ACPR measurement. For all specifications, both DACA and DACB are measured and the lowest value used as the specification. Figure 25. DAC5682Z Test Configuration for Normal Clock Mode Adjacent Carrier Leakage Ratio (ACLR): Defined for a 3.84Mcps 3GPP W-CDMA input signal measured in a 3.84MHz bandwidth at a 5MHz offset from the carrier with a 12dB peak-to-average ratio. Analog and Digital Power Supply Rejection Ratio (APSSR, DPSSR): Defined as the percentage error in the ratio of the delta IOUT and delta supply voltage normalized with respect to the ideal IOUT current. Differential Nonlinearity (DNL): Defined as the variation in analog output associated with an ideal 1 LSB change in the digital input code. Gain Drift: Defined as the maximum change in gain, in terms of ppm of full-scale range (FSR) per °C, from the value at ambient (25°C) to values over the full operating temperature range. Gain Error: Defined as the percentage error (in FSR%) for the ratio between the measured full-scale output current and the ideal full-scale output current. Integral Nonlinearity (INL): Defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero scale to full scale. Intermodulation Distortion (IMD3, IMD): The two-tone IMD3 or four-tone IMD is defined as the ratio (in dBc) of the worst 3rd-order (or higher) intermodulation distortion product to either fundamental output tone. 18 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): DAC5682Z |
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