DAC5682Z datasheet(28/59 Pages) TI

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DAC5682Z

SLLS853C – AUGUST 2007 – REVISED JUNE 2009 ........................................................................................................................................................ www.ti.com

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

PLL_LPF_ reset

VCO_div2

PLL_gain(1:0)

PLL_range(3:0)

PLL_LPF_reset:

When a logic high, the PLL loop filter (LPF) is pulled down to 0V. Toggle from ‘1’ to ‘0’ to

restart the PLL if an over-speed lock-up occurs. Over-speed can happen when the process

is fast, the supplies are higher than nominal, etc., resulting in the feedback dividers missing

a clock.

VCO_div2:

When set, the PLL CLOCK output is 1/2 the PLL VCO frequency. Used to run the VCO at

2X the needed clock frequency to reduce phase noise for lower input clock rates.

PLL_gain(1:0):

Used to adjust the PLL’s Voltage Controlled Oscillator (VCO) gain, KVCO. Refer to the

Electrical Characteristics table. By increasing the PLL_gain, the VCO can cover a broader

range of frequencies; however, the higher gain also increases the phase noise of the PLL.

In general, lower PLL_gain settings result in lower phase noise. The KVCO of the VCO can

also affect the PLL stability and is used to determine the loop filter components. See

section on determining the PLL filter components for more detail.

PLL_range(3:0):

Programs the PLL VCO fixed bias current. Refer to the Electrical Characteristics table. This

setting, in conjunction with the PLL_gain(1:0), sets the achievable frequency range of the

PLL VCO:

'000' – minimum bias current and lowest VCO frequency range

'111' – maximum bias current and highest VCO frequency range

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved(1:0)

Offset_sync

OffsetA(12:8)

Reserved(1:0):

Set to ‘00’ for proper operation.

Offset_sync:

On a change from ‘0’ to ‘1’ the values of the OffsetA(12:0) and OffsetB(12:0) control

registers are transferred to the registers used in the DAC-A and DAC-B offset calculations.

This double buffering allows complete control by the user as to when the change in the

offset value occurs. This bit does not auto-clear. Prior to updating new offset values, it is

recommended that the user clear this bit.

OffsetA(12:8):

Upper 5 bits of the offset adjustment value for the A data path. (SYNCED via Offset_sync)

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

OffsetA(7:0)

OffsetA(7:0):

Lower 8 bits of the offset adjustment value for the A data path. (SYNCED via Offset_sync)

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