EP2C50 datasheet(16/34 Pages) ALTERA

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Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Functional Description

Configuration Handbook (Complete Two-Volume Set)

Altera Corporation

2. Using VPP < VPPLK, where the maximum value of VPPLK is 1 V, disables writes.

VPP < VPPLK means programming or writes cannot occur. VPP is a programming

supply voltage input pin on the Intel flash. VPP is equivalent to the VCCW pin on

EPC devices.

3. Using a high CE# disables the chip. The requirement for a write is a low CE# and

low WE#. A high CE# by itself prevents writes from occurring.

4. Using a high WE# prevent writes because a write only occurs when the WE# is low.

Performing all four methods simultaneously is the safest protection for the flash

content.

The ideal power-up sequence is as follows:

1. Power-up VCC .

2. Maintain VPP < VPPLK until VCC is fully powered up.

3. Power-up VPP .

4. Drive RP# low during the entire power-up process. RP# must be released high

within 25 ms after VPP is powered up.

1 CE# and WE# must be high for the entire power-up sequence.

The ideal power-down sequence is as follows:

1. Drive RP# low for 100ns before power-down.

2. Power-down VPP < VPPLK.

3. Power-down VCC.

4. Drive RP# low during the entire power-down process.

1 CE# and WE# must be high for the entire power-down sequence.

The RP# pin is not internally connected to the controller. Therefore, an external

loop-back connection between C-RP# and F-RP# must be made on the board even

when you are not using the external device to the RP# pin with the loop-back. Always

tri-state RP# when the flash is not in use.

If an external power-up monitoring circuit is connected to the RP# pin with the

loop-back, use the following guidelines to avoid contention on the RP# line:

■

The power-up sequence on the 3.3-V supply should complete within 50 ms of

power-up. The 3.3-V VCC should reach the minimum VCC before 50 ms and RP#

should then be released.

■ RP#

should be driven low by the power-up monitoring circuit during power-up.

After power-up, RP# should be tri-stated externally by the power-up monitoring

circuit.

If the preceding guidelines cannot be completed within 50 ms, then the OE pin must

be driven low externally until RP# is ready to be released.

EP2C50 Datasheet(PDF) 16 Page - Altera Corporation

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