EP2C50 datasheet(2/34 Pages) ALTERA

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Chapter 1: Enhanced Configuration Devices (EPC4, EPC8, and EPC16) Data Sheet

Functional Description

Configuration Handbook (Complete Two-Volume Set)

Altera Corporation

■

Supports ISP via Jam Standard Test and Programming Language (STAPL)

■

Supports JTAG boundary scan

■ nINIT

_CONF pin allows private JTAG instruction to start FPGA configuration

■

Internal pull-up resistor on nINIT_CONF always enabled

■

User programmable weak internal pull-up resistors on nCS and OE pins

■

Internal weak pull-up resistors on external flash interface address and control

lines, bus hold on data lines

■

Standby mode with reduced power consumption

f For more information about FPGA configuration schemes and advanced features,

refer to the appropriate FPGA family chapter in the Configuration Handbook.

Functional Description

The Altera enhanced configuration device is a single-device, high-speed, advanced

configuration solution for very high-density FPGAs. The core of an enhanced

configuration device is divided into two major blocks: a configuration controller and a

flash memory. The flash memory is used to store configuration data for systems made

up of one or more Altera FPGAs. Unused portions of the flash memory can be used to

store processor code or data that can be accessed via the external flash interface after

FPGA configuration is complete. Table 1–1 summarizes the features of Altera

configuration devices and the amount of configuration space they hold.

Table 1–2 lists the supported configuration devices required to configure an ACEX 1K,

APEX 1K, APEX 20K, APEX 20KC, APEX 20KE, APEX II, Arria GX, Cyclone,

Cyclone II, FLEX 10K, FLEX 10KA, FLEX 10KE, Stratix, Stratix GX, Stratix II, Stratix II

GX, or Mercury device.

Table 1–1. Altera Configuration Devices

Device

Memory Size

(bits)

On-Chip

Decompression

Support

ISP

Support

Cascading

Support

Reprogrammable

Operating

Voltage (V)

EPC4

4,194,304

Yes

3.3

EPC8

8,388,608

Yes

3.3

EPC16

16,777,216

Yes

3.3

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