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Preliminary
2-4
RF3321
Rev A10 010516
3
Serial Bus Block Diagram
Pin
Function
Description
Interface Schematic
1
SHDNB
Chip shutdown pin. Forcing a logic low causes all circuits to switch off
andgainsettingstobelost.
2TX EN
Signal path enable pin. Logic high turns on signal path. Logic low turns
off signal path, but leaves serial bus active.
3NC
Not connected.
4VIN
Input pin. This should be externally AC-coupled to signal source.
5VINB
Complementary input pin. This should be externally coupled to signal
source. For single-ended use, this pin should be AC-coupled to ground.
See pin 4.
6
VCC1
This pinis connectedtoVCC1.
7
VCC1
Same as pin 6.
8
RAMP
External capacitor to ground controls start-up time.
9SCLK
Serial bus clock input.
10
CS
Serial bus enable.
11
SDA
Serial bus data input.
12
VOUTB
Open collector output. Connect to VCC2 via balun primary.
13
VOUT
Open collector output. Connect to VCC2 via balun primary.
See pin 12.
14
NC
Same as pin 3.
15
NC
Same as pin 3.
16
GND
Connect to ground.
PKG
BASE
GND
Die is mounted on a heat sink slug that should be connected to ground.
Device grounds are internally bonded to the slug.
550
Ω
550
Ω
V
CC
500
Ω
500
Ω
V
INB
V
IN
300
Ω
V
OUT
V
OUTB
RE
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D
CK
Q
CLR
D0
D1
D2
D3
D4
D5
D6
POR
CS
SDA
SCLK
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