KM416RD8ACD-RK80 datasheet(47/64 Pages) SAMSUNG

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KM416RD8AC(D)/KM418RD8AC(D)

Direct RDRAM™

Rev. 1.01 Oct. 1999

Electrical Conditions

Timing Conditions

Table 18: Electrical Conditions

Symbol

Parameter and Conditions

Min

Max

Unit

Junction temperature under bias

100

°C

VDD, VDDA

Supply voltage

2.50 - 0.13

2.50 + 0.13

VDD,N, VDDA,N

Supply voltage droop (DC) during NAP interval (tNLIMIT)

2.0

vDD,N, vDDA,N

Supply voltage ripple (AC) during NAP interval (tNLIMIT)

-2.0

2.0

VCMOS

Supply voltage for CMOS pins (2.5V controllers)

2.50 - 0.13

2.50 + 0.25

Supply voltage for CMOS pins (1.8V controllers)

1.80 - 0.1

1.80 + 0.2

VTERM

Termination voltage

1.80 - 0.1

1.80 + 0.1

VREF

Reference voltage

1.40 - 0.2

1.40 + 0.2

VDIL

RSL data input - low voltage

VREF - 0.5

VREF - 0.2

VDIH

RSL data input - high voltage

VREF + 0.2

VREF + 0.5

VDIS

RSL data input swing: VDIS = VDIH - VDIL

0.4

1.0

ADI

RSL data asymmetry: ADI = [(VDIH - VREF) + (VDIL - VREF)]/VDIS

-20

RSL clock input - crossing point of true and complement signals

1.3

1.8

VCM

RSL clock input - common mode VCM = (VCIH+VCIL)/2

1.4

1.7

VCIS,CTM

RSL clock input swing: VCIS = VCIH - VCIL (CTM,CTMN pins).

0.35

0.70

VCIS,CFM

RSL clock input swing: VCIS = VCIH - VCIL (CFM,CFMN pins).

0.125

0.70

VIL,CMOS

CMOS input low voltage

- 0.3

VCMOS/2 - 0.25

VIH,CMOS

CMOS input high voltage

VCMOS/2 + 0.25

VCMOS+0.3

Table 19: Timing Conditions

Symbol

Parameter

Min

Max

Unit

Figure(s)

tCYCLE

CTM and CFM cycle times (-600)

3.33

3.83

Figure 53

CTM and CFM cycle times (-711)

2.80

3.83

Figure 53

CTM and CFM cycle times (-800)

2.50

3.83

Figure 53

tCR, tCF

CTM and CFM input rise and fall times

0.2

0.5

Figure 53

tCH, tCL

CTM and CFM high and low times

40%

60%

tCYCLE

Figure 53

tTR

CTM-CFM differential (MSE/MS=0/0)

CTM-CFM differential (MSE/MS=1/1)a

0.0

0.9

1.0

tCYCLE

Figure 42

Figure 53

tDCW

Domain crossing window

-0.1

0.1

tCYCLE

Figure 59

tDR, tDF

DQA/DQB/ROW/COL input rise/fall times

0.2

0.65

Figure 54

tS, tH

DQA/DQB/ROW/COL-to-CFM setup/hold @ tCYCLE=3.33ns

@ tCYCLE=2.81ns

@tCYCLE=2.50ns

0.275b,d

0.240c,d

0.200d

Figure 54

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