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Device Address

1

1

1

0

A1

A2

A0

Slave Address

R/W

Fixed

Hardware

Selectable

Control Register

Channel Selection Bits

(Read/Write)

Channel 0

Channel 1

Channel 2

Channel 3

B3

B2

B1

B0

3

2

1

0

X

X

X

X

4

5

6

7

Control Register Definition

PCA9546A

WITH RESET FUNCTION

SCPS148E – OCTOBER 2005 – REVISED JANUARY 2008

Following a start condition, the bus master must output the address of the slave it is accessing. The address of

the PCA9546A is shown in Figure 1. To conserve power, no internal pullup resistors are incorporated on the

hardware-selectable address pins, and they must be pulled high or low.

Figure 1. PCA9546A Address

The last bit of the slave address defines the operation to be performed. When set to a logic 1, a read is selected,

while a logic 0 selects a write operation.

Following the successful acknowledgment of the slave address, the bus master sends a byte to the PCA9546A,

which is stored in the control register (see Figure 2). If multiple bytes are received by the PCA9546A, it will save

Figure 2. Control Register

One or several SCn/SDn downstream pairs, or channels, are selected by the contents of the control register (see

Table 1). This register is written after the PCA9546A has been addressed. The four LSBs of the control byte are

used to determine which channel or channels are to be selected. When a channel is selected, the channel

a high state when the channel is made active, so that no false conditions are generated at the time of

connection. A stop condition always must occur right after the acknowledge cycle.

4

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