TAS5715PHPR datasheet(49/74 Pages) TI

49 / 74 page

TAS5715

www.ti.com

SLOS645 – AUGUST 2010

Table 3. Serial Control Interface Register Summary (continued)

NO. OF

INITIALIZATION

SUBADDRESS

CONTENTS

BYTES

VALUE

0x34

ch2_bq[4]

u[31:26], b0[25:0]

0x0080 0000

u[31:26], b1[25:0]

0x0000 0000

u[31:26], b2[25:0]

0x0000 0000

u[31:26], a1[25:0]

0x0000 0000

u[31:26], a2[25:0]

0x0000 0000

0x35

ch2_bq[5]

u[31:26], b0[25:0]

0x0080 0000

u[31:26], b1[25:0]

0x0000 0000

u[31:26], b2[25:0]

0x0000 0000

u[31:26], a1[25:0]

0x0000 0000

u[31:26], a2[25:0]

0x0000 0000

0x36

ch2_bq[6]

u[31:26], b0[25:0]

0x0080 0000

u[31:26], b1[25:0]

0x0000 0000

u[31:26], b2[25:0]

0x0000 0000

u[31:26], a1[25:0]

0x0000 0000

u[31:26], a2[25:0]

0x0000 0000

0x37

EQ CRC

u[31:16], EQ CRC [15:0]

0x0000 A14C

0x38

DRC CRC

u[31:16], DRC CRC [15:0]

0x0000 5395

0x39

Reserved(2)

0x0000 0000

0x3A

Reserved(2)

0x0080 0000

0x3B

DRC1 softening filter alpha

u[31:26], ae[25:0]

0x0008 0000

DRC1 softening filter

u[31:26], oe[25:0]

0x0078 0000

omega

0x3C

DRC1 attack rate

0x0000 0100

DRC1 release rate

0xFFFF FF00

0x3D

Reserved(2)

0x0080 0000

0x3E

DRC2 softening filter alpha

u[31:26], ae[25:0]

0x0008 0000

DRC2 softening filter

u[31:26], oe[25:0]

0xFFF8 0000

omega

0x3F

DRC2 attack rate

u[31:26], at[25:0]

0x0008 0000

DRC2 release rate

u[31:26], rt[25:0]

0xFFF8 0000

0x40

DRC1 attack threshold

T1[31:0] (9.23 format)

0x0800 0000

DRC1 release threshold

T1'[31:0]

0x07FF FFFF

0x42

Reserved(2)

0x0000 0000

0x43

DRC2 attack threshold

T2[31:0] (9.23 format)

0x0074 0000

DRC2 release threshold

T2'[31:0]

0x0073 FFFF

0x45

Reserved(2)

0x0000 0000

0x46

DRC and DC DETECT

Description shown in subsequent section

0x0002 0020

control

0x47–0x4F

Reserved(2)

0x50

Bank switch control

Description shown in subsequent section

0x0F70 8000

0x51

Ch 1 output mixer

Ch 1 output mix1[1]

0x0080 0000

Ch 1 output mix1[0]

0x0000 0000

0x52

Ch 2 output mixer

Ch 2 output mix2[1]

0x0080 0000

Ch 2 output mix2[0]

0x0000 0000

0x53

Ch 1 input mixers

Channel-1 input mixers can be accessed using I2C

subaddresses 0x70–0x73 using 4-byte access

(2)

Reserved registers should not be accessed.

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