TAS5715PHPR datasheet(59/74 Pages) TI

59 / 74 page

TAS5715

www.ti.com

SLOS645 – AUGUST 2010

MODULATION LIMIT REGISTER (0x10)

Table 15. Modulation Limit Register (0x10)

MODULATION LIMIT

–

Reserved

–

99.2%

–

98.4% (1)

–

97.7%

–

96.9%

–

96.1%

–

95.3%

–

94.5%

–

93.8%

(1)

Default values are in bold.

INTERCHANNEL DELAY REGISTERS (0x11, 0x12, 0x13, and 0x14)

Internal PWM Channels 1, 2, 1, and 2 are mapped into registers 0x11, 0x12, 0x13, and 0x14.

Table 16. Channel Interchannel Delay Register Format

BIT DEFINITION

FUNCTION

–

Minimum absolute delay, 0 DCLK cycles

–

Maximum positive delay, 31 × 4 DCLK cycles

–

Maximum negative delay, –32 × 4 DCLK cycles

Reserved

SUBADDRESS

Delay = (value) × 4 DCLKs

0x11

–

Default value for channel 1 (1)

0x12

–

Default value for channel 2 (1)

0x13

–

Default value for channel 1 (1)

0x14

–

Default value for channel 2 (1)

(1)

Default values are in bold.

ICD settings have high impact on audio performance (e.g.: dynamic range, THD, crosstalk, etc.) Therefore,

appropriate ICD settings must be used. By default, the device has ICD settings for AD mode. If used in BD

mode, then update these registers before coming out of all-channel shutdown.

MODE

AD MODE

BD MODE

0x11

0x12

0x13

0x14

Submit Documentation Feedback

Product Folder Link(s): TAS5715

TAS5715PHPR Datasheet(PDF) 59 Page - Texas Instruments

TAS5715PHPR Datasheet(HTML) 59 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74

Datasheet Download

Link URL