PIC18LF4331-ESLASHML datasheet(232/392 Pages) MICROCHIP

232 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 232

 2010 Microchip Technology Inc.

20.3.5

BREAK CHARACTER SEQUENCE

The Enhanced USART module has the capability of

sending the special Break character sequences that

are required by the LIN/J2602 bus standard. The Break

character transmit consists of a Start bit, followed by

twelve ‘0’ bits and a Stop bit. The Frame Break charac-

ter is sent whenever the SENDB and TXEN bits

(TXSTA<3> and TXSTA<5>) are set while the Transmit

Shift register is loaded with data. Note that the value of

data written to TXREG will be ignored and all ‘0’s will

be transmitted.

The SENDB bit is automatically reset by hardware after

the corresponding Stop bit is sent. This allows the user

to preload the transmit FIFO with the next transmit byte

following the Break character (typically, the Sync

character in the LIN/J2602 specification).

Note that the data value written to the TXREG for the

Break character is ignored. The write simply serves the

purpose of initiating the proper sequence.

The TRMT bit indicates when the transmit operation is

active or Idle, just as it does during normal transmis-

sion. See Figure 20-9 for the timing of the Break

character sequence.

20.3.5.1

Break and Sync Transmit Sequence

The following sequence will send a message frame

header made up of a Break, followed by an Auto-Baud

Sync byte. This sequence is typical of a LIN/J2602 bus

master.

Configure the EUSART for the desired mode.

Set the TXEN and SENDB bits to setup the

Break character.

Load the TXREG with a dummy character to

initiate transmission (the value is ignored).

Write ‘55h’ to TXREG to load the Sync character

into the transmit FIFO buffer.

After the Break has been sent, the SENDB bit is

reset by hardware. The Sync character now

transmits in the preconfigured mode.

When the TXREG becomes empty, as indicated by the

TXIF, the next data byte can be written to TXREG.

20.3.6

RECEIVING A BREAK CHARACTER

The Enhanced USART module can receive a Break

character in two ways.

The first method forces configuration of the baud rate

at a frequency of 9/13 of the typical speed. This allows

for the Stop bit transition to be at the correct sampling

location (13 bits for Break versus Start bit and 8 data

bits for typical data).

The second method uses the auto-wake-up feature

described in Section 20.3.4 “Auto-Wake-up on Sync

Break Character”

. By enabling this feature, the

EUSART will sample the next two transitions on RX/DT,

cause an RCIF interrupt and receive the next data byte

followed by another interrupt.

Note that following a Break character, the user will

typically want to enable the Auto-Baud Rate Detect

feature. For both methods, the user can set the ABD bit

before placing the EUSART in its Sleep mode.

FIGURE 20-9:

SEND BREAK CHARACTER SEQUENCE

Write to TXREG

BRG Output

(Shift Clock)

Start Bit

Bit 0

Bit 1

Bit 11

Stop Bit

Break

TXIF bit

(Interrupt Reg. Flag)

TX (Pin)

TRMT bit

(Transmit Shift

Reg. Empty Flag)

SENDB

(Transmit Shift

Reg. Empty Flag)

SENDB sampled here

Auto-Cleared

Dummy Write

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