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PIC18LF4331-E/ML Datasheet(PDF) 257 Page - Microchip Technology |
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PIC18LF4331-E/ML Datasheet(HTML) 257 Page - Microchip Technology |
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257 / 392 page ![]() 2010 Microchip Technology Inc. DS39616D-page 257 PIC18F2331/2431/4331/4431 22.0 LOW-VOLTAGE DETECT (LVD) PIC18F2331/2431/4331/4431 devices have a Low- Voltage Detect module (LVD), a programmable circuit that enables the user to specify a device voltage trip point. If the device experiences an excursion below the trip point, an interrupt flag is set. If the interrupt is enabled, the program execution will branch to the inter- rupt vector address and the software can then respond to the interrupt. The Low-Voltage Detect Control register (Register 22-1) completely controls the operation of the LVD module. This allows the circuitry to be “turned off” by the user under software control, which minimizes the current consumption for the device. The block diagram for the LVD module is shown in Figure 22-1. The module is enabled by setting the LVDEN bit, but the circuitry requires some time to stabilize each time that it is enabled. The IRVST bit is a read-only bit used to indicate when the circuit is stable. The module can only generate an interrupt after the circuit is stable and the IRVST bit is set. The module monitors for drops in VDD below a predetermined set point. REGISTER 22-1: LVDCON: LOW-VOLTAGE DETECT CONTROL REGISTER U-0 U-0 R-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 — — IRVST LVDEN LVDL3(1) LVDL2(1) LVDL1(1) LVDL0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 7-6 Unimplemented: Read as ‘0’ bit 5 IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the Low-Voltage Detect logic will generate the interrupt flag at the specified voltage range 0 = Indicates that the Low-Voltage Detect logic will not generate the interrupt flag at the specified voltage range and the LVD interrupt should not be enabled bit 4 LVDEN: Low-Voltage Detect Power Enable bit 1 = Enables LVD, powers up LVD circuit 0 = Disables LVD, powers down LVD circuit bit 3-0 LVDL<3:0>: Low-Voltage Detection Limit bits(1) 1111 = External analog input is used (input comes from the LVDIN pin) 1110 = Maximum setting . . . 0010 = Minimum setting 0001 = Reserved 0000 = Reserved Note 1: LVDL<3:0> bit modes, which result in a trip point below the valid operating voltage of the device, are not tested. |
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