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PIC18LF4331-E/ML Datasheet(PDF) 255 Page - Microchip Technology |
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PIC18LF4331-E/ML Datasheet(HTML) 255 Page - Microchip Technology |
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255 / 392 page  2010 Microchip Technology Inc. DS39616D-page 255 PIC18F2331/2431/4331/4431 TABLE 21-3: SUMMARY OF A/D REGISTERS Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset Values on Page: INTCON GIE/GIEH PEIE/GIEL TMR0IE INT0IE RBIE TMR0IF INT0IF RBIF 54 PIR1 —ADIF RCIF TXIF SSPIF CCP1IF TMR2IF TMR1IF 57 PIE1 —ADIE RCIE TXIE SSPIE CCP1IE TMR2IE TMR1IE 57 IPR1 —ADIP RCIP TXIP SSPIP CCP1IP TMR2IP TMR1IP 57 PIR2 OSCFIF — — EEIF — LVDIF — CCP2IF 57 PIE2 OSCFIE — — EEIE — LVDIE — CCP2IE 57 IPR2 OSCFIP — — EEIP — LVDIP — CCP2IP 57 ADRESH A/D Result Register High Byte 56 ADRESL A/D Result Register Low Byte 56 ADCON0 — — ACONV ACSCH ACMOD1 ACMOD0 GO/DONE ADON 56 ADCON1 VCFG1 VCFG0 — FIFOEN BFEMT BFOVFL ADPNT1 ADPNT0 56 ADCON2 ADFM ACQT3 ACQT2 ACQT1 ACQT0 ADCS2 ADCS1 ADCS0 56 ADCON3 ADRS1 ADRS0 — SSRC4 SSRC3 SSRC2 SSRC1 SSRC0 56 ADCHS GDSEL1 GDSEL0 GBSEL1 GBSEL0 GCSEL1 GCSEL0 GASEL1 GASEL0 56 ANSEL0 ANS7(6) ANS6(6) ANS5(6) ANS4 ANS3 ANS2 ANS1 ANS0 56 ANSEL1 — — — — — — —ANS8(5) 56 PORTA RA7(4) RA6(4) RA5 RA4 RA3 RA2 RA1 RA0 57 TRISA TRISA7(4) TRISA6(4) PORTA Data Direction Register 57 PORTE(2) — — — — RE3(1,3) RA2(3) RA1(3) RA0(3) 57 TRISE(3) — — — — — PORTE Data Direction Register 57 LATE(3) — — — — — LATE Data Output Register 57 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used for A/D conversion. Note 1: The RE3 port bit is available only as an input pin when the MCLRE bit in the CONFIG3H register is ‘0’. 2: This register is not implemented on PIC18F2331/2431 devices. 3: These bits are not implemented on PIC18F2331/2431 devices. 4: These pins may be configured as port pins depending on the oscillator mode selected. 5: ANS5 through ANS8 are available only on the PIC18F4331/4431 devices. 6: Not available on 28-pin devices. |
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