PIC18LF4331-ESLASHML datasheet(268/392 Pages) MICROCHIP

268 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 268

 2010 Microchip Technology Inc.

CONFIG3H: CONFIGURATION REGISTER 3 HIGH (BYTE ADDRESS 300005h)

R/P-1

MCLRE(1)

—

—EXCLKMX(1) PWM4MX(1)

SSPMX(1)

—FLTAMX(1)

bit 7

bit 0

Legend:

R = Readable bit

P = Programmable bit

U = Unimplemented bit, read as ‘0’

-n = Value when device is unprogrammed

U = Unchanged from programmed state

bit 7

MCLRE:

MCLR Pin Enable bit(1)

=MCLR pin is enabled; RE3 input pin is disabled

= RE3 input pin is enabled; MCLR is disabled

bit 6-5

Unimplemented:

Read as ‘0’

bit 4

EXCLKMX:

TMR0/T5CKI External Clock MUX bit(1)

= TMR0/T5CKI external clock input is multiplexed with RC3

= TMR0/T5CKI external clock input is multiplexed with RD0

bit 3

PWM4MX:

PWM4 MUX bit(1)

= PWM4 output is multiplexed with RB5

= PWM4 output is multiplexed with RD5

bit 2

SSPMX:

SSP I/O MUX bit(1)

= SCK/SCL clocks and SDA/SDI data are multiplexed with RC5 and RC4, respectively. SDO output

is multiplexed with RC7.

= SCK/SCL clocks and SDA/SDI data are multiplexed with RD3 and RD2, respectively. SDO output

is multiplexed with RD1.

bit 1

Unimplemented:

Read as ‘0’

bit 0

FLTAMX:

FLTA MUX bit(1)

=FLTA input is multiplexed with RC1

=FLTA input is multiplexed with RD4

Note 1:

Unimplemented in PIC18F2331/2431 devices; maintain this bit set.

PIC18LF4331-E/ML Datasheet(PDF) 268 Page - Microchip Technology

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