PIC18LF4331-ESLASHML datasheet(274/392 Pages) MICROCHIP

274 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 274

 2010 Microchip Technology Inc.

23.2

Watchdog Timer (WDT)

For PIC18F2331/2431/4331/4431 devices, the WDT is

driven by the INTRC source. When the WDT is

enabled, the clock source is also enabled. The nominal

WDT period is 4 ms and has the same stability as the

INTRC oscillator.

The 4 ms period of the WDT is multiplied by a 16-bit

postscaler. Any output of the WDT postscaler is

selected by a multiplexer, controlled by bits in

Configuration

(see

Available periods range from 4 ms to 131.072 seconds

(2.18 minutes). The WDT and postscaler are cleared

when any of the following events occur: execute a

SLEEP

or CLRWDT instruction, the IRCF bits

(OSCCON<6:4>) are changed or a clock failure has

occurred (see Section 23.4.1 “FSCM and the

Watchdog Timer”

Adjustments to the internal oscillator clock period using

the OSCTUNE register also affect the period of the

WDT by the same factor. For example, if the INTRC

period is increased by 3%, then the WDT period is

increased by 3%.

23.2.1

CONTROL REGISTER

readable and writable register. The SWDTEN bit allows

software to enable or disable the WDT, but only if the

Configuration bit has disabled the WDT. The WDTW bit

is a read-only bit that indicates when the WDT count is

in the fourth quadrant (i.e., when the 8-bit WDT value is

’11000000’ or greater).

FIGURE 23-1:

WDT BLOCK DIAGRAM

Note 1:

The CLRWDT and SLEEP instructions

clear the WDT and postscaler counts

when executed.

Changing the setting of the IRCF bits

(OSCCON<6:4>) clears the WDT and

postscaler counts.

When a CLRWDT instruction is executed,

the postscaler count will be cleared.

If WINEN = 0, then CLRWDT must be exe-

cuted only when WDTW = 1; otherwise, a

device Reset will result.

INTRC Source

WDT

Wake-up

Reset

WDT

WDT Counter

Programmable Postscaler

1:1 to 1:32,768

Enable WDT

WDTPS<3:0>

SWDTEN

WDTEN

CLRWDT

from Sleep

Reset

All Device Resets

Sleep

INTRC Control

125

Change on IRCF bits

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