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PIC18LF4331-E/ML Datasheet(PDF) 346 Page - Microchip Technology |
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PIC18LF4331-E/ML Datasheet(HTML) 346 Page - Microchip Technology |
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346 / 392 page  PIC18F2331/2431/4331/4431 DS39616D-page 346 2010 Microchip Technology Inc. 26.4.3 TIMING DIAGRAMS AND SPECIFICATIONS FIGURE 26-5: EXTERNAL CLOCK TIMING (ALL MODES EXCEPT PLL) TABLE 26-4: EXTERNAL CLOCK TIMING REQUIREMENTS Param. No. Symbol Characteristic Min Max Units Conditions 1A FOSC External CLKI Frequency(1) DC 40 MHz EC, ECIO Oscillator Frequency(1) DC 4 MHz RC osc 0.1 4 MHz XT osc 4 25 MHz HS osc 4 10 MHz HS + PLL osc 5 200 kHz LP Osc mode 1TOSC External CLKI Period(1) 25 — ns EC, ECIO Oscillator Period(1) 250 — ns RC osc 250 10,000 ns XT osc 25 100 250 250 ns ns HS osc HS + PLL osc 25 — sLP osc 2TCY Instruction Cycle Time(1) 100 — ns TCY = 4/FOSC 3 TosL, TosH External Clock in (OSC1) High or Low Time 30 — ns XT osc 2.5 — sLP osc 10 — ns HS osc 4TosR, TosF External Clock in (OSC1) Rise or Fall Time — 20 ns XT osc — 50 ns LP osc —7.5 ns HS osc Note 1: Instruction cycle period (TCY) equals four times the input oscillator time base period for all configurations except PLL. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. OSC1 CLKO Q4 Q1 Q2 Q3 Q4 Q1 1 2 3 3 4 4 |
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