PIC18LF4331-ESLASHML datasheet(102/392 Pages) MICROCHIP

102 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 102

 2010 Microchip Technology Inc.

10.2

PIR Registers

The PIR registers contain the individual flag bits for the

peripheral interrupts. Due to the number of peripheral

interrupt sources, there are three Peripheral Interrupt

Request (Flag) Registers (PIR1, PIR2 and PIR3).

Note 1:

Interrupt flag bits are set when an inter-

rupt condition occurs, regardless of the

state of its corresponding enable bit or the

Global

Interrupt

Enable

bit,

GIE

(INTCON<7>).

User software should ensure the appro-

priate interrupt flag bits are cleared prior

to enabling an interrupt and after servicing

that interrupt.

PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1

U-0

R/W-0

R-0

R/W-0

—

ADIF

RCIF

TXIF

SSPIF

CCP1IF

TMR2IF

TMR1IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented:

Read as ‘0’

bit 6

ADIF:

A/D Converter Interrupt Flag bit

= An A/D conversion completed (must be cleared in software)

= The A/D conversion is not complete

bit 5

RCIF:

EUSART Receive Interrupt Flag bit

= The EUSART receive buffer, RCREG, is full (cleared when RCREG is read)

= The EUSART receive buffer is empty

bit 4

TXIF:

EUSART Transmit Interrupt Flag bit

= The EUSART transmit buffer, TXREG, is empty (cleared when TXREG is written)

= The EUSART transmit buffer is full

bit 3

SSPIF:

Synchronous Serial Port Interrupt Flag bit

= The transmission/reception is complete (must be cleared in software)

= Waiting to transmit/receive

bit 2

CCP1IF:

CCP1 Interrupt Flag bit

Capture mode:

= A TMR1 register capture occurred (must be cleared in software)

= No TMR1 register capture occurred

Compare mode:

= A TMR1 register compare match occurred (must be cleared in software)

= No TMR1 register compare match occurred

PWM mode:

Unused in this mode.

bit 1

TMR2IF:

TMR2 to PR2 Match Interrupt Flag bit

= TMR2 to PR2 match occurred (must be cleared in software)

= No TMR2 to PR2 match occurred

bit 0

TMR1IF:

TMR1 Overflow Interrupt Flag bit

= TMR1 register overflowed (must be cleared in software)

= TMR1 register did not overflow

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