PIC18LF4331-ESLASHML datasheet(147/392 Pages) MICROCHIP

147 / 392 page

 2010 Microchip Technology Inc.

DS39616D-page 147

PIC18F2331/2431/4331/4431

16.4

Compare Mode

In Compare mode, the 16-bit CCPR1 (CCPR2) register

value is constantly compared against the TMR1

CCP1 (RC1/CCP2) pin:

• is driven high

• is driven low

• toggles output (high-to-low or low-to-high)

• remains unchanged (interrupt only)

The action on the pin is based on the value of control

bits, CCP1M<3:0> (CCP2M<3:0>). At the same time,

interrupt flag bit CCP1IF (CCP2IF) is set.

16.4.1

CCP PIN CONFIGURATION

The user must configure the CCP1 pin as an output by

clearing the appropriate TRISC bit.

16.4.2

TIMER1 MODE SELECTION

Timer1 must be running in Timer mode or Synchro-

nized Counter mode if the CCP module is using the

compare feature. In Asynchronous Counter mode, the

compare operation may not work.

16.4.3

SOFTWARE INTERRUPT MODE

When generate software interrupt is chosen, the CCP1

pin is not affected. Only a CCP interrupt is generated (if

enabled).

16.4.4

SPECIAL EVENT TRIGGER

In this mode, an internal hardware trigger is generated

which may be used to initiate an action.

The Special Event Trigger output of CCP1 resets the

TMR1 register pair. This allows the CCPR1 register to

effectively be a 16-bit programmable period register for

Timer1.

The Special Event Trigger output of CCP2 resets the

TMR1 register pair. Additionally, the CCP2 Special

Event Trigger will start an A/D conversion if the A/D

module is enabled.

FIGURE 16-2:

COMPARE MODE OPERATION BLOCK DIAGRAM

Note:

Clearing the CCPxCON register will force

the RC1 or RC2 compare output latch to

the default low level. This is not the

PORTC I/O data latch.

Note:

The Special Event Trigger from the CCP2

module will not set the Timer1 interrupt

flag bit.

CCPR1H CCPR1L

TMR1H

TMR1L

Comparator

Output

Logic

Special Event Trigger

Set Flag CCP1IF bit

Match

RC2/CCP1 Pin

TRISC<2>

CCP1CON<3:0>

Mode Select

Output Enable

Special Event Trigger will:

Reset Timer1, but not set Timer1 interrupt flag bit

and set bit, GO/DONE (ADCON0<1>), which starts an A/D conversion (CCP2 only)

CCPR2H CCPR2L

Comparator

Output

Logic

Special Event Trigger

Set Flag CCP2IF bit

Match

RC1/CCP2 Pin

TRISC<1>

CCP2CON<3:0>

Mode Select

Output Enable

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