PIC18LF4331-ESLASHML datasheet(169/392 Pages) MICROCHIP

169 / 392 page

 2010 Microchip Technology Inc.

DS39616D-page 169

PIC18F2331/2431/4331/4431

17.3

Noise Filters

The Motion Feedback Module includes three noise

rejection

filters

RA2/AN2/VREF-/CAP1/INDX,

RA3/AN3/VREF+/CAP2/QEA and RA4/AN4/CAP3/QEB.

The filter block also includes a fourth filter for the T5CKI

pin. They are intended to help reduce spurious noise

spikes which may cause the input signals to become

corrupted at the inputs. The filter ensures that the input

signals are not permitted to change until a stable value

has been registered for three consecutive sampling

clock cycles.

The filters are controlled using the Digital Filter Control

(DFLTCON) register (see Register 17-3). The filters

can be individually enabled or disabled by setting or

clearing the corresponding FLTxEN bit in the

DFLTCON register. The sampling frequency, which

must be the same for all three noise filters, can be

programmed by the FLTCK<2:0> Configuration bits.

TCY is used as the clock reference to the clock divider

block.

The noise filters can either be added or removed from

the input capture, or QEI signal path, by setting or

clearing the appropriate FLTxEN bit, respectively. Each

capture channel provides for individual enable control

of the filter output. The FLT4EN bit enables or disables

the noise filter available on the T5CKI input in the

Timer5 module.

The filter network for all channels is disabled on

Power-on and Brown-out Resets, as the DFLTCON

is shown in the timing diagram in Figure 17-14.

DFLTCON: DIGITAL FILTER CONTROL REGISTER

U-0

R/W-0

—

FLT4EN

FLT3EN(1)

FLT2EN(1)

FLT1EN(1)

FLTCK2

FLTCK1

FLTCK0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7

Unimplemented:

Read as ‘0’

bit 6

FLT4EN:

Noise Filter Output Enable bit (T5CKI input)

= Enabled

= Disabled

bit 5

FLT3EN:

Noise Filter Output Enable bit (CAP3/QEB input)(1)

= Enabled

= Disabled

bit 4

FLT2EN:

Noise Filter Output Enable bit (CAP2/QEA input)(1)

= Enabled

= Disabled

bit 3

FLT1EN:

Noise Filter Output Enable bit (CAP1/INDX Input)(1)

= Enabled

= Disabled

bit 2-0

FLTCK<2:0>:

Noise Filter Clock Divider Ratio bits

111

= Unused

110

= 1:128

101

= 1:64

100

= 1:32

011

= 1:16

010

= 1:4

001

= 1:2

000

= 1:1

Note 1:

The noise filter output enables are functional in both QEI and IC Operating modes.

Note:

The noise filter is intended for random high-frequency filtering and not continuous high-frequency filtering.

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