PIC18LF4331-ESLASHML datasheet(170/392 Pages) MICROCHIP

170 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 170

 2010 Microchip Technology Inc.

FIGURE 17-14:

NOISE FILTER TIMING DIAGRAM (CLOCK DIVIDER = 1:1)

17.4

IC and QEI Shared Interrupts

The IC and QEI submodules can each generate three

distinct interrupt signals; however, they share the use

of the same three interrupt flags in register, PIR3. The

meaning of a particular interrupt flag at any given time

depends on which module is active at the time the

interrupt is set. The meaning of the flags in context are

summarized in Table 17-7.

When the IC submodule is active, the three flags (IC1IF,

IC2QEIF and IC3DRIF) function as interrupt-on-capture

event flags for their respective input capture channels.

The channel must be configured for one of the events

that will generate an interrupt (see Section 17.1.7 “IC

Interrupts”

for more information).

When the QEI is enabled, the IC1IF interrupt flag

indicates

interrupt

caused

velocity

measurement event, usually an update of the VELR

measurement event has occurred. IC3DRIF indicates

that a direction change has been detected.

TABLE 17-7:

MEANING OF IC AND QEI

INTERRUPT FLAGS

17.5

Operation in Sleep Mode

17.5.1

3x INPUT CAPTURE IN SLEEP

MODE

Since the input capture can operate only when its time

base is configured in a Synchronous mode, the input

capture will not capture any events. This is because the

device’s internal clock has been stopped and any inter-

nal timers in Synchronous modes will not increment.

The prescaler will continue to count the events (not

synchronized).

When the specified capture event occurs, the CAPx

interrupt will be set. The Capture Buffer register will be

updated upon wake-up from sleep to the current TMR5

value. If the CAPx interrupt is enabled, the device will

wake-up from Sleep. This effectively enables all input

capture channels to be used as the external interrupts.

17.5.2

QEI IN SLEEP MODE

All QEI functions are halted in Sleep mode.

CAP1/INDX Pin(1)

TCY

Noise Glitch(3)

CAP1/INDX Input(2)

TQEI = 16 TCY

Note 1:

Only the CAP1/INDX pin input is shown for simplicity. Similar event timing occurs on the CAP2/QEA and

CAP3/QEB pins.

Noise filtering occurs in the shaded portions of the CAP1 input.

Filter’s group delay: TGD = 3 TCY.

(input to filter)

(output from filter) TGD = 3 TCY

Noise Glitch(3)

Interrupt

Flag

Meaning

IC Mode

QEI Mode

IC1IF

IC1 Capture Event Velocity Register Update

IC2QEIF IC2 Capture Event

Position Measurement

Update

IC3DRIF IC3 Capture Event

Direction Change

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