PIC18LF4331-ESLASHML datasheet(191/392 Pages) MICROCHIP

191 / 392 page

 2010 Microchip Technology Inc.

DS39616D-page 191

PIC18F2331/2431/4331/4431

18.7

Dead-Time Generators

In power inverter applications, where the PWMs are

used in Complementary mode to control the upper and

lower switches of a half-bridge, a dead-time insertion is

highly recommended. The dead-time insertion keeps

both outputs in inactive state for a brief time. This

avoids any overlap in the switching during the state

change of the power devices due to TON and TOFF

characteristics.

Because the power output devices cannot switch

instantaneously, some amount of time must be pro-

vided between the turn-off event of one PWM output in

a complementary pair and the turn-on event of the

other transistor. The PWM module allows dead time to

be programmed. The following sections explain the

dead-time block in detail.

18.7.1

DEAD-TIME INSERTION

Each complementary output pair for the PWM module

has a 6-bit down counter used to produce the

dead-time insertion. As shown in Figure 18-17, each

dead-time unit has a rising and falling edge detector

connected to the duty cycle comparison output. The

dead time is loaded into the timer on the detected PWM

edge event. Depending on whether the edge is rising or

falling, one of the transitions on the complementary

outputs is delayed until the timer counts down to zero.

A timing diagram, indicating the dead-time insertion for

one pair of PWM outputs, is shown in Figure 18-18.

FIGURE 18-17:

DEAD-TIME CONTROL UNIT BLOCK DIAGRAM FOR ONE PWM OUTPUT PAIR

FIGURE 18-18:

DEAD-TIME INSERTION FOR COMPLEMENTARY PWM

Even PWM Signal to

Output Control Block

Odd PWM Signal to

Output Control Block

Zero Compare

Clock Control

and Prescaler

6-Bit Down Counter

Duty Cycle

Compare Input

Dead Time

Prescale

FOSC

Dead Time

Select Bits

Dead-Time Register

PDC1

Compare

Output

PWM1

PWM0

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