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PIC18LF4331-E/ML Datasheet(PDF) 194 Page - Microchip Technology |
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PIC18LF4331-E/ML Datasheet(HTML) 194 Page - Microchip Technology |
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194 / 392 page ![]() PIC18F2331/2431/4331/4431 DS39616D-page 194 2010 Microchip Technology Inc. 18.8.2 PWM CHANNEL OVERRIDE PWM output may be manually overridden for each PWM channel by using the appropriate bits in the OVDCOND and OVDCONS registers. The user may select the following signal output options for each PWM output pin operating in the Independent PWM mode: • I/O pin outputs PWM signal • I/O pin inactive • I/O pin active Refer to Section 18.10 “PWM Output Override” for details for all the override functions. FIGURE 18-19: CENTER CONNECTED LOAD 18.9 Single-Pulse PWM Operation The single-pulse PWM operation is available only in Edge-Aligned mode. In this mode, the PWM module will produce single-pulse output. Single-pulse operation is configured when the PTMOD<1:0> bits are set to ‘01’ in the PTCON0 register. This mode of operation is useful for driving certain types of ECMs. In Single-Pulse mode, the PWM I/O pin(s) are driven to the active state when the PTEN bit is set. When the PWM timer match with the Duty Cycle register occurs, the PWM I/O pin is driven to the inactive state. When the PWM timer match with the PTPER register occurs, the PTMR register is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared and an interrupt is generated if the corresponding interrupt bit is set. 18.10 PWM Output Override The PWM output override bits allow the user to manu- ally drive the PWM I/O pins to specified logic states, independent of the duty cycle comparison units. The PWM override bits are useful when controlling various types of ECMs like a BLDC motor. OVDCOND and OVDCONS registers are used to define the PWM override options. The OVDCOND register contains eight bits, POVD<7:0>, that determine which PWM I/O pins will be overridden. The OVDCONS register contains eight bits, POUT<7:0>, that determine the state of the PWM I/O pins when a particular output is overridden via the POVD bits. The POVD bits are active-low control bits. When the POVD bits are set, the corresponding POUT bit will have no effect on the PWM output. In other words, the pins corresponding to POVD bits that are set will have the duty PWM cycle set by the PDCx registers. When one of the POVD bits is cleared, the output on the cor- responding PWM I/O pin will be determined by the state of the POUT bit. When a POUT bit is set, the PWM pin will be driven to its active state. When the POUT bit is cleared, the PWM pin will be driven to its inactive state. 18.10.1 COMPLEMENTARY OUTPUT MODE The even numbered PWM I/O pins have override restrictions when a pair of PWM I/O pins are operating in the Complementary mode (PMODx = 0). In Comple- mentary mode, if the even numbered pin is driven active by clearing the corresponding POVD bit and by setting POUT bits in the OVDCOND and OVDCONS registers, the output signal is forced to be the comple- ment of the odd numbered I/O pin in the pair (see Figure 18-2 for details). 18.10.2 OVERRIDE SYNCHRONIZATION If the OSYNC bit in the PWMCON1 register is set, all output overrides performed via the OVDCOND and OVDCONS registers will be synchronized to the PWM time base. Synchronous output overrides will occur on the following conditions: • When the PWM is in Edge-Aligned mode, synchronization occurs when PTMR is zero. • When the PWM is in Center-Aligned mode, synchronization occurs when PTMR is zero and when the value of PTMR matches PTPER. Note: PTPER and PDCx values are held as they are after the single-pulse output. To have another cycle of single pulse, only PTEN has to be enabled. +V PWM1 PWM0 Load Note 1: In the Complementary mode, the even channel cannot be forced active by a Fault or override event when the odd channel is active. The even channel is always the complement of the odd channel with dead time inserted, before the odd channel can be driven to its active state, as shown in Figure 18-20. 2: Dead time is inserted in the PWM channels even when they are in Override mode. |
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