PIC18LF4331-ESLASHML datasheet(198/392 Pages) MICROCHIP

198 / 392 page

PIC18F2331/2431/4331/4431

DS39616D-page 198

 2010 Microchip Technology Inc.

18.11 PWM Output and Polarity Control

There are three device Configuration bits associated

with the PWM module that provide PWM output pin

control defined in the CONFIG3L Configuration

•HPOL

•LPOL

•PWMPIN

These three Configuration bits work in conjunction with

the three PWM Enable bits (PWMEN<2:0>) in the

PWMCON0 register. The Configuration bits and PWM

enable bits ensure that the PWM pins are in the correct

states after a device Reset occurs.

18.11.1

OUTPUT PIN CONTROL

The PWMEN<2:0> control bits enable each PWM

output pin as required in the application.

All PWM I/O pins are general purpose I/O. When a pair

of pins are enabled for PWM output, the PORT and

TRIS registers controlling the pins are disabled. Refer

to Figure 18-23 for details.

18.11.2

OUTPUT POLARITY CONTROL

The polarity of the PWM I/O pins is set during device

programming via the HPOL and LPOL Configuration

bits in the CONFIG3L Configuration register. The

HPOL Configuration bit sets the output polarity for the

high side PWM outputs: PWM1, PWM3, PWM5 and

PWM7. The polarity is active-low when HPOL is

cleared (= 0), and active-high when it is set (= 1).

The LPOL Configuration bit sets the output polarity for

the low side PWM outputs: PWM0, PWM2, PWM4 and

PWM6. As with HPOL, they are active-low when LPOL

is cleared and active-high when it is set.

All output signals generated by the PWM module are

referenced to the polarity control bits, including those

generated by Fault inputs or manual override (see

Section 18.10 “PWM Output Override”

The default polarity Configuration bits have the PWM

I/O pins in active-high output polarity.

FIGURE 18-23:

PWM I/O PIN BLOCK DIAGRAM

Data Bus

WR PORT

WR TRIS

RD PORT

Data Latch

TRIS Latch

VSS

I/O Pin

VDD

RD TRIS

Schmitt

Trigger

TTL or

PWM Pin Enable

PWM Signal from Module

Note:

I/O pin has protection diodes to VDD and VSS. PWM polarity selection logic not shown for clarity.

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