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ISL6334DIRZ Datasheet(PDF) 27 Page - Intersil Corporation |
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ISL6334DIRZ Datasheet(HTML) 27 Page - Intersil Corporation |
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27 / 28 page ![]() 27 All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN6802.2 August 31, 2010 Component Placement Within the allotted implementation area, orient the switching components first. The switching components are the most critical because they carry large amounts of energy and tend to generate high levels of noise. Switching component placement should take into account power dissipation. Align the output inductors and MOSFETs such that space between the components is minimized while creating the PHASE plane. Place the Intersil MOSFET driver IC as close as possible to the MOSFETs they control to reduce the parasitic impedances due to trace length between critical driver input and output signals. If possible, duplicate the same placement of these components for each phase. Next, place the input and output capacitors. Position one high frequency ceramic input capacitor next to each upper MOSFET drain. Place the bulk input capacitors as close to the upper MOSFET drains, as dictated by the component size and dimensions. Long distances between input capacitors and MOSFET drains result in too much trace inductance and a reduction in capacitor performance. Locate the output capacitors between the inductors and the load, while keeping them in close proximity to the microprocessor socket. Voltage-Regulator (VR) Design Materials The tolerance band calculation (TOB) worksheets for VR output regulation and IMON have been developed using the Root-Sum-Squared (RSS) method with 3 sigma distribution point of the related components and parameters. Note that the “Electrical Specifications” table beginning on page 6 specifies no less than 6 sigma distribution point, not suitable for RSS TOB calculation. Intersil also developed a set of worksheets to support VR design and layout. Contact Intersil’s local office or field support for the latest available information. ISL6334D |
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