G35 datasheet(5/351 Pages) INTEL

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Datasheet

5.1.17

DMIBAR—Root Complex Register Range Base Address ..................92

5.1.18

PAM0—Programmable Attribute Map 0........................................93

5.1.19

PAM1—Programmable Attribute Map 1........................................95

5.1.20

PAM2—Programmable Attribute Map 2........................................96

5.1.21

PAM3—Programmable Attribute Map 3........................................97

5.1.22

PAM4—Programmable Attribute Map 4........................................98

5.1.23

PAM5—Programmable Attribute Map 5........................................99

5.1.24

PAM6—Programmable Attribute Map 6...................................... 100

5.1.25

LAC—Legacy Access Control.................................................... 101

5.1.26

REMAPBASE—Remap Base Address Register.............................. 102

5.1.27

REMAPLIMIT—Remap Limit Address Register ............................. 102

5.1.28

SMRAM—System Management RAM Control .............................. 103

5.1.29

ESMRAMC—Extended System Management RAM Control ............. 104

5.1.30

TOM—Top of Memory............................................................. 105

5.1.31

TOUUD—Top of Upper Usable Dram ......................................... 106

5.1.32

GBSM—Graphics Base of Stolen Memory................................... 107

5.1.33

TSEGMB—TSEG Memory Base ................................................. 107

5.1.34

TOLUD—Top of Low Usable DRAM............................................ 108

5.1.35

ERRSTS—Error Status ............................................................ 109

5.1.36

ERRCMD—Error Command...................................................... 110

5.1.37

SMICMD—SMI Command........................................................ 111

5.1.38

SKPD—Scratchpad Data ......................................................... 111

5.1.39

CAPID0—Capability Identifier .................................................. 112

5.2

MCHBAR ........................................................................................... 113

5.2.1

CHDECMISC—Channel Decode Miscellaneous............................. 116

5.2.2

C0DRB0—Channel 0 DRAM Rank Boundary Address 0................. 117

5.2.3

C0DRB1—Channel 0 DRAM Rank Boundary Address 1................. 118

5.2.4

C0DRB2—Channel 0 DRAM Rank Boundary Address 2................. 119

5.2.5

C0DRB3—Channel 0 DRAM Rank Boundary Address 3................. 119

5.2.6

C0DRA01—Channel 0 DRAM Rank 0,1 Attribute ......................... 120

5.2.7

C0DRA23—Channel 0 DRAM Rank 2,3 Attribute ......................... 121

5.2.8

C0CYCTRKPCHG—Channel 0 CYCTRK PCHG............................... 121

5.2.9

C0CYCTRKACT—Channel 0 CYCTRK ACT ................................... 122

5.2.10

C0CYCTRKWR—Channel 0 CYCTRK WR ..................................... 123

5.2.11

C0CYCTRKRD—Channel 0 CYCTRK READ................................... 124

5.2.12

C0CYCTRKREFR—Channel 0 CYCTRK REFR ................................ 124

5.2.13

C0CKECTRL—Channel 0 CKE Control ........................................ 125

5.2.14

C0REFRCTRL—Channel 0 DRAM Refresh Control......................... 126

5.2.15

C0ODTCTRL—Channel 0 ODT Control ....................................... 128

5.2.16

C1DRB0—Channel 1 DRAM Rank Boundary Address 0................. 129

5.2.17

C1DRB1—Channel 1 DRAM Rank Boundary Address 1................. 129

5.2.18

C1DRB2—Channel 1 DRAM Rank Boundary Address 2................. 130

5.2.19

C1DRB3—Channel 1 DRAM Rank Boundary Address 3................. 130

5.2.20

C1DRA01—Channel 1 DRAM Rank 0,1 Attributes........................ 131

5.2.21

C1DRA23—Channel 1 DRAM Rank 2,3 Attributes........................ 131

5.2.22

C1CYCTRKPCHG—Channel 1 CYCTRK PCHG............................... 132

5.2.23

C1CYCTRKACT—Channel 1 CYCTRK ACT ................................... 133

5.2.24

C1CYCTRKWR—Channel 1 CYCTRK WR ..................................... 134

5.2.25

C1CYCTRKRD—Channel 1 CYCTRK READ................................... 135

5.2.26

C1CKECTRL—Channel 1 CKE Control ........................................ 136

5.2.27

C1REFRCTRL—Channel 1 DRAM Refresh Control......................... 137

5.2.28

C1ODTCTRL—Channel 1 ODT Control ....................................... 139

5.2.29

EPC0DRB0—ME Channel 0 DRAM Rank Boundary Address 0........ 140

5.2.30

EPC0DRB1—ME Channel 0 DRAM Rank Boundary Address 1 ........ 140

5.2.31

EPC0DRB2— ME Channel 0 DRAM Rank Boundary Address 2........ 141

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