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Thermal Specifications and Design Considerations

Datasheet

5.1.4

Digital Thermal Sensor

The Celeron M processor also contains an on die digital thermal sensor that can be read

via a MSR (no I/O interface). The digital thermal sensor is the preferred method of

reading the processor die temperature since it can be located much closer to the

hottest portions of the die and can thus more accurately track the die temperature and

potential activation of processor core clock modulation via the Intel Thermal Monitor.

The digital thermal sensor is only valid while the processor is in the normal operating

state (C0 state).

Unlike traditional thermal devices, the Digital Thermal sensor will output a temperature

relative to the maximum supported operating temperature of the processor (TJ,max). It

is the responsibility of software to convert the relative temperature to an absolute

temperature. The temperature returned by the digital thermal sensor will always be at

or below TJ,max. Over temperature conditions are detectable via an Out Of Spec status

bit. This bit is also part of the Digital Thermal sensor MSR. When this bit is set, the

processor is operating out of specification and immediate shutdown of the system

should occur. The processor operation and code execution is not guaranteed once the

activation of the Out of Spec status bit is set.

The Digital Thermal Sensor (DTS) relative temperature readout corresponds to the

Intel Thermal Monitor (TM1) trigger point. When the DTS indicates maximum processor

core temperature has been reached TM1 hardware thermal control mechanism will

activate. The DTS and Intel Thermal Monitor (TM1) temperature may not correspond to

the thermal diode reading since the thermal diode is located in a separate portion of

the die and thermal gradient between the individual core DTS. Additionally, the thermal

gradient from DTS to thermal diode can vary substantially due to changes in processor

power, mechanical and thermal attach and software application. The system designer is

required to use the DTS to guarantee proper operation of the processor within its

temperature operating specifications.

Changes to the temperature can be detected via two programmable thresholds located

in the processor MSRs. These thresholds have the capability of generating interrupts

via the core's local APIC. Refer to the IA-32 Intel® Architecture Software Developer's

Manual and your Intel representative for specific register and programming details.

5.1.5

Out of Specification Detection

Overheat detection is performed by monitoring the processor temperature and

temperature gradient. This feature is intended for graceful shut down before the

THERMTRIP# is activated. If the processor’s TM1 is triggered and the temperature

remains high, an “Out Of Spec” status and sticky bit are latched in the status MSR

contact your Intel representative.

5.1.6

PROCHOT# Signal Pin

An external signal, PROCHOT# (processor hot), is asserted when the processor die

temperature has reached its maximum operating temperature. If the Intel Thermal

Monitor 1 is enabled (note that the Intel Thermal Monitor 1 must be enabled for the

processor to be operating within specification), the TCC will be active when PROCHOT#

is asserted. The processor can be configured to generate an interrupt upon the

assertion or deassertion of PROCHOT#. Refer to the IA-32 Intel® Architecture Software

Developer's Manuals and your Intel representative for specific register and

programming details.

The Celeron M processor implements a bi-directional PROCHOT# capability to allow

system designs to protect various components from over-temperature situations. The

PROCHOT# signal is bi-directional in that it can either signal when the processor has

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