IXP45X datasheet(31/148 Pages) INTEL

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Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

August 2006

Datasheet

Document Number: 306261-004US

Datasheet—Intel® IXP45X and Intel® IXP46X Product Line of Network Processors

3.1.21

Queue Manager

The Queue Manager provides a means for maintaining coherency for data handling

between various processors cores contained on the IXP45X/IXP46X network processors

(NPE to NPE, NPE to Intel XScale® processor, etc.). It maintains the queues as circular

buffers in an embedded 8-Kbyte SRAM. The Queue Manager also implements the status

flags and pointers required for each queue.

The Queue Manager manages 64 independent queues. Each queue is configurable for

buffer and entry size. Additionally status flags are maintained for each queue.

The Queue Manager interfaces include an Advanced High-performance Bus (AHB)

interface to the NPEs and Intel XScale® processor (or any other AHB bus master), a

Flag Bus interface, an event bus (to the NPE condition select logic), and two interrupts

to the Intel XScale® processor.

The AHB interface is used for configuration of the Queue Manager and provides access

to queues, queue status, and SRAM. Individual queue status for queues 0-31 is

communicated to the NPEs via the flag bus. Combined queue status for queues 32-63

are communicated to the NPEs via the event bus. The two interrupts, one for queues 0-

31 and one for queues 32-63, provide status interrupts to the Intel XScale® processor.

3.2

Intel XScale® Processor

The Intel XScale technology is compliant with the Intel® StrongARM* Version 5TE

instruction-set architecture (ISA). The Intel XScale® processor, shown in Figure 4, is

designed with Intel, 0.18-micron production semiconductor process technology. This

process technology — with the compactness of the Intel® StrongARM* RISC ISA —

enables the Intel XScale® processor to operate over a wide speed and power range,

producing industry-leading mW/MIPS performance.

Intel XScale® processor features include:

• Seven/eight-stage super-pipeline promotes high-speed, efficient performance

• 128-entry branch target buffer keeps pipeline filled with statistically correct branch

choices

• 32-entry instruction memory-management unit for logical-to-physical address

translation, access permissions, and Instruction-Cache (I-cache) attributes

• 32-entry data-memory management unit for logical-to-physical address

translation, access permissions, Data-Cache (D-Cache) attributes

• 32-Kbyte instruction cache can hold entire programs, preventing processor stalls

caused by multi-cycle memory accesses

• 32-Kbyte data cache reduces processor stalls caused by multi-cycle memory

accesses

• 2-Kbyte mini-data cache for frequently changing data streams avoids “thrashing”

of the D-cache

• Four-entry, fill-and-pend buffers to promote processor efficiency by allowing “hit-

under-miss” operation with data caches

• Eight-entry write buffer allows the processor to continue execution while data is

written to memory

• Multiple-accumulate coprocessor that can do two simultaneous, 16-bit, SIMD

multiplies with 40-bit accumulation for efficient, high-quality media and signal

processing

• Performance monitoring unit (PMU) furnishing two 32-bit event counters and one

32-bit cycle counter for analysis of hit rates, etc.

IXP45X Datasheet(PDF) 31 Page - Intel Corporation

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