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PSD813F2V Datasheet(PDF) 71 Page - STMicroelectronics |
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PSD813F2V Datasheet(HTML) 71 Page - STMicroelectronics |
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71 / 109 page ![]() Obsolete Product(s) - Obsolete Product(s) 71/109 PSD813F2V, PSD854F2V Doc ID 10552 Rev 3 INITIAL DELIVERY STATE When delivered from ST, the PSD device has all bits in the memory and PLDs set to ’1.’ The PSD Configuration Register bits are set to ’0.’ The code, configuration, and PLD logic are loaded using the programming procedure. Information for program- ming the device is available directly from ST. Please contact your local sales representative. Table 35. JTAG Enable Register Note: 1. The state of Reset (RESET) does not interrupt (or prevent) JTAG operations if the JTAG signals are dedicated by an NVM Config- uration bit (via PSDsoft Express). However, Reset (RESET) prevents or interrupts JTAG operations if the JTAG enable register is used to enable the JTAG signals. Bit 0 JTAG_Enable 0 = off JTAG port is disabled. 1 = on JTAG port is enabled. Bit 1 X 0 Not used, and should be set to zero. Bit 2 X 0 Not used, and should be set to zero. Bit 3 X 0 Not used, and should be set to zero. Bit 4 X 0 Not used, and should be set to zero. Bit 5 X 0 Not used, and should be set to zero. Bit 6 X 0 Not used, and should be set to zero. Bit 7 X 0 Not used, and should be set to zero. |
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