PSD813F2V datasheet(98/109 Pages) STMICROELECTRONICS

98 / 109 page

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Product(s)

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Product(s)

PSD813F2V, PSD854F2V

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Doc ID 10552 Rev 3

Table 68. ISC Timing (3V devices)

Note: 1. For non-PLD Programming, Erase or in ISC by-pass mode.

2. For Program or Erase PLD only.

Table 69. Power-down Timing (5V devices)

Note: 1. tCLCL is the period of CLKIN (PD1).

Table 70. Power-down Timing (3V devices)

Note: 1. tCLCL is the period of CLKIN (PD1).

Symbol

Parameter

Conditions

-12

-15

-20

Unit

MinMax

tISCCF

Clock (TCK, PC1) Frequency (except for

PLD)

(Note 1)

MHz

tISCCH

Clock (TCK, PC1) High Time (except for

PLD)

(Note 1)

tISCCL

Clock (TCK, PC1) Low Time (except for

PLD)

(Note 1)

tISCCFP

Clock (TCK, PC1) Frequency (PLD only)

(Note 2)

222

MHz

tISCCHP

Clock (TCK, PC1) High Time (PLD only)

(Note 2)

240

tISCCLP

Clock (TCK, PC1) Low Time (PLD only)

(Note 2)

240

tISCPSU

ISC Port Set Up Time

tISCPH

ISC Port Hold Up Time

tISCPCO

ISC Port Clock to Output

tISCPZV

ISC Port High-Impedance to Valid Output

tISCPVZ

ISC Port Valid Output to

High-Impedance

Symbol

Parameter

Conditions

-70

-90

-15

Unit

MinMax

tLVDV

ALE Access Time from Power-down

150

tCLWH

Maximum Delay from

APD Enable to Internal PDN Valid

Signal

Using CLKIN

(PD1)

15 * tCLCL

µs

Symbol

Parameter

Conditions

-12

-15

-20

Unit

MinMax

tLVDV

ALE Access Time from Power-down

145

150

200

tCLWH

Maximum Delay from APD Enable to

Internal PDN Valid Signal

Using CLKIN

(PD1)

15 * tCLCL

µs

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