W77LE532 datasheet(13/88 Pages) WINBOND

13 / 88 page

W77LE532/W77L532A

Publication Release Date: February 1, 2007

- 13 -

Revision A7

TIMER CONTROL

Bit:

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Mnemonic: TCON

Address: 88h

TF1:

Timer 1 overflow flag: This bit is set when Timer 1 overflows. It is cleared automatically when

the program does a timer 1 interrupt service routine. Software can also set or clear this bit.

TR1:

Timer 1 run control: This bit is set or cleared by software to turn timer/counter on or off.

TF0:

Timer 0 overflow flag: This bit is set when Timer 0 overflows. It is cleared automatically when

the program does a timer 0 interrupt service routine. Software can also set or clear this bit.

TR0:

Timer 0 run control: This bit is set or cleared by software to turn timer/counter on or off.

IE1:

Interrupt 1 edge detect: Set by hardware when an edge/level is detected on INT1. This bit is

cleared by hardware when the service routine is vectored to only if the interrupt was edge

triggered. Otherwise it follows the pin.

IT1:

Interrupt 1 type control: Set/cleared by software to specify falling edge/ low level triggered

external inputs.

IE0:

Interrupt 0 edge detect: Set by hardware when an edge/level is detected on INT0 . This bit is

cleared by hardware when the service routine is vectored to only if the interrupt was edge

triggered. Otherwise it follows the pin.

IT0:

Interrupt 0 type control: Set/cleared by software to specify falling edge/ low level triggered

external inputs.

TIMER MODE CONTROL

Bit:

GATE

TIMER1

TIMER0

Mnemonic: TMOD

Address: 89h

GATE: Gating control: When this bit is set, Timer/counter x is enabled only while INTx pin is high and

TRx control bit is set. When cleared, Timer x is enabled whenever TRx control bit is set.

: Timer or Counter Select: When cleared, the timer is incremented by internal clocks. When set

, the timer counts high-to-low edges of the Tx pin.

W77LE532 Datasheet(PDF) 13 Page - Winbond

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