W77LE532 datasheet(21/88 Pages) WINBOND

21 / 88 page

W77LE532/W77L532A

Publication Release Date: February 1, 2007

- 21 -

Revision A7

SLAVE ADDRESS

Bit:

Mnemonic: SADDR

Address: A9h

SADDR: The SADDR should be programmed to the given or broadcast address for serial port 0 to

which the slave processor is designated.

SLAVE ADDRESS 1

Bit:

Mnemonic: SADDR1

Address: AAh

SADDR1: The SADDR1 should be programmed to the given or broadcast address for serial port 1 to

which the slave processor is designated.

ROM BANKING CONTROL

Bit:

EN128K DCP12 DCP11 DCP10

Mnemonic: ROMCON

Address: ABh

EN128K: On-chip ROM banking enable. Set this bit to enable APFLASH0 and APFLASH1 by banking

mechanism. The P1.x is selected to be the auxiliary highest address line A16.

DCP1x: A16 selection. By default, P1.7 is defined as A16.

A16

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

DCP12

DCP11

DCP10

ISP ADDRESS LOW BYTE

Bit:

Mnemonic: SFRAL

Address: ACh

Low byte destination address for In System Programming operations. SFRAH and SFRAL address a

specific ROM bytes for erasure, porgramming or read.

W77LE532 Datasheet(PDF) 21 Page - Winbond

W77LE532 Datasheet(HTML) 21 Page - Winbond

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