IR3831MPBF datasheet(16/31 Pages) IRF

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11/05/10

IR3831MPbF

IR3831

Vin

When an external resistor divider is connected to

the output as shown in figure 10.

Equation (5) can be rewritten as:

For low voltage applications, such as this

design, it is often advisable to eliminate the bias

resistor R9 from Fb to ground. For the calculated

value of R8 see feedback compensation section.

Further, the tracking reference Vp may be itself

derived from some master reference by means

of a resistive divider as shown in Fig. 9. This is

common in active bus termination circuits such

as Voltage Tracking Termination (VTT) where

the tracking reference Vp may be obtained as

half of the master reference VDDQ which forms

the input to one or more memory banks.

In this design,

VDDQ=1.5V

p1=Rp2=1.5 kΩ

Vp=0.75V

Soft-Start Programming

The soft-start timing can be programmed by

selecting the soft-start capacitance value. From

(1), for a desired start-up time of the converter,

the soft start capacitor can be calculated by

using:

Where T

start is the desired start-up time (ms).

For tracking applications the output is generally

required to track Vp even at start-up. Hence, it is

necessary to ensure that the SS pin is already

up to 3 V before the tracking reference signal is

applied to the Vp pin. This can be done by

choosing a small value for the soft-start

capacitor to ensure that the voltage at the SS pin

rises to 3 V quickly. A 0.022 uF capacitor is

chosen for this purpose.

Application Information

Design Example:

The following example is a typical application for

IR3831. The application circuit is shown on page

22.

Enabling the IR3831

As explained earlier, the precise threshold of

the Enable lends itself well to implementation of

a UVLO for the Bus Voltage.

For a typical Enable threshold of V

EN = 1.2 V

For a V

in (min)=10.2V, R1=4.99K and R2=750 ohm

is a good choice.

Programming the frequency

For F

s = 400 kHz, select Rt = 35.7 kΩ, using

Table. 1.

Output Voltage Programming

Output voltage is programmed by the tracking

reference voltage at Vp and external voltage

divider. The divider is ratioed such that the

voltage at the Fb pin is equal to the voltage at the

Vp pin pin when the output is at its desired value.

The output voltage is defined by using the

following equation:

kHz

400

22.5mV

0.75

max)

13.2V

(

ΔV

≤

.....(7)

..........

⎟⎟

⎠

⎞

⎜⎜

⎝

⎛

∗

Fig. 10. Typical application of the IR3831 for

programming the output voltage

(8)

....

..........

⎟

⎠

⎞

⎜

⎝

⎛

−

∗

start

(9)

..........

0.02857

)

(

)

μF

(

Enable

(5)

..........

1.2

(min)

)

in(

(6)

..........

min

−

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