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PPC8567ECVTAQGGA Datasheet(PDF) 97 Page - Freescale Semiconductor, Inc |
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PPC8567ECVTAQGGA Datasheet(HTML) 97 Page - Freescale Semiconductor, Inc |
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97 / 139 page  MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1 Freescale Semiconductor 97 HDLC, BISYNC, Transparent and Synchronous UART Figure 65 provides the AC test load. Figure 65. AC Test Load Outputs—Internal clock High Impedance tHIKHOX 05.5 ns Outputs—External clock High Impedance tHEKHOX 18 ns Inputs—Internal clock input setup time tHIIVKH 6— ns Inputs—External clock input setup time tHEIVKH 4— ns Inputs—Internal clock input Hold time tHIIXKH 0— ns Inputs—External clock input hold time tHEIXKH 1— ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Table 77. Synchronous UART AC Timing Specifications Characteristic Symbol 2 Min Max Unit Outputs—Internal clock delay tHIKHOV 011 ns Outputs—External clock delay tHEKHOV 114 ns Outputs—Internal clock High Impedance tHIKHOX 011 ns Outputs—External clock High Impedance tHEKHOX 114 ns Inputs—Internal clock input setup time tHIIVKH 6— ns Inputs—External clock input setup time tHEIVKH 8— ns Inputs—Internal clock input Hold time tHIIXKH 0— ns Inputs—External clock input hold time tHEIXKH 1— ns Notes: 1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings are measured at the pin. 2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X). Table 76. HDLC, BiSync, Transparent AC Timing Specifications 1 (continued) Characteristic Symbol 2 Min Max Unit Output Z0 = 50 Ω OVDD/2 RL = 50 Ω |
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