PPC8567CVTAUJGA datasheet(68/139 Pages) FREESCALE

68 / 139 page

MPC8568E/MPC8567E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 1

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 46 shows the SerDes reference clock connection reference circuits for LVPECL type clock driver.

Since LVPECL driver’s DC levels (both common mode voltages and output swing) are incompatible with

MPC8568 SerDes reference clock input’s DC requirement, AC-coupling has to be used. Figure 46

assumes that the LVPECL clock driver’s output impedance is 50

Ω. R1 is used to DC-bias the LVPECL

outputs prior to AC-coupling. Its value could be ranged from 140

Ω to 240Ω depending on clock driver

vendor’s requirement. R2 is used together with the SerDes reference clock receiver’s 50-

Ω termination

resistor to attenuate the LVPECL output’s differential peak level such that it meets the MPC8568 SerDes

reference clock’s differential input amplitude requirement (between 200mV and 800mV differential peak).

For example, if the LVPECL output’s differential peak is 900mV and the desired SerDes reference clock

input amplitude is selected as 600mV, the attenuation factor is 0.67, which requires R2 = 25

Ω. Consult

clock driver chip manufacturer to verify whether this connection scheme is compatible with a particular

clock driver chip.

Figure 46. AC-Coupled Differential Connection with LVPECL Clock Driver (Reference Only)

SD_REF_CLK

Clock Driver

100

Ω differential PWB trace

SerDes Refer.

CLK Receiver

Clock Driver

CLK_Out

LVPECL CLK

Driver Chip

MPC8568E

10 nF

PPC8567CVTAUJGA Datasheet(PDF) 68 Page - Freescale Semiconductor, Inc