M48T201Y datasheet(22/37 Pages) STMICROELECTRONICS

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Clock operation

M48T201Y, M48T201V

22/37

3.8

Power-on reset

The M48T201Y/V continuously monitors VCC. When VCC falls to the power fail detect trip

point, the RST pulls low (open drain) and remains low on power-up for tREC after VCC

passes VPFD (max). The RST pin is an open drain output and an appropriate pull-up resistor

to VCC should be chosen to control rise time.

3.9

Reset inputs (RSTIN1 & RSTIN2)

The M48T201Y/V provides two independent inputs which can generate an output reset. The

duration and function of these resets is identical to a reset generated by a power cycle.

Figure 9 and Table 8 illustrate the AC reset characteristics of this function. Pulses shorter

than tR1 and tR2 will not generate a reset condition. RSTIN1 and RSTIN2 are each internally

pulled up to VCC through a 100 KΩ resistor.

Figure 9.

RSTIN1 and RSTIN2 timing waveforms

Table 8.

Reset AC characteristics

3.10

Calibrating the clock

The M48T201Y/V is driven by a quartz controlled oscillator with a nominal frequency of

32,768 Hz. The devices are factory calibrated at 25°C and tested for accuracy. Clock

accuracy will not exceed ±35 ppm (parts per million) oscillator frequency error at 25°C,

which equates to about ±1.53 minutes per month. When the calibration circuit is properly

employed, accuracy improves to better than +1/–2 ppm at 25°C.

Symbol

Parameter(1)

Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.5 to 5.5 V or 3.0 to 3.6 V (except where

noted).

Min

Max

Unit

tR1

RSTIN1 low to RST low

200

tR2

RSTIN2 low to RST low

100

tR1HRZ

(2)

CL = 5 pF (see Figure 13 on page 28).

RSTIN1 high to RST Hi-Z

200

tR2HRZ

(2)

RSTIN2 high to RST Hi-Z

200

AI01679

RSTIN1

RST

RSTIN2

tR1

tR1HRZ

Hi-Z

tR2

tR2HRZ

Hi-Z

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