Dual SPM Detector

Page 4 of 16

MX641 Preliminary Information

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2. Signal List

Pin

No.

Name

Type

Description

1

Xtal/Clock

input

The input to the on-chip clock oscillator; for use with a 3.579545MHz

Xtal in conjunction with the Xtal output; circuit components are on-chip.

When using a Xtal input, the Clock Out pin should be connected directly

to the Clock In pin. If a clock pulse input is used at the Clock In pin, this

Figure 3 for details of clock frequency distribution.

2

XTAL

output

The output of the on-chip clock oscillator inverter.

3

Clock Out

output

The buffered output of the on-chip-clock oscillator inverter. If a Xtal

input is used, this output should be connected directly to the Clock In

pin. This output can support up to 3 additional MX641 ICs. See Figure

3 for details of clock frequency distribution.

4

Clock In

input

The 3.579545 clock pulse input to the internal clock dividers. If an

externally generated clock pulse input is used, the Xtal/Clock input pin

5

Enable

Output

input

For multi-chip output multiplexing; controls the state of both Ch1 and

Ch2 outputs. When this input is placed high (logic '1') both outputs are

set to a high impedance. When placed low (logic '0') both outputs are

enabled.

6

Ch 2 Output

output

The digital output of the Channel 2 SPM detector when enabled. The

format of the signal at this pin, in common with Ch 1, is selectable to

either 'Tone Follower' or 'Packet' mode via the Output Select input.

7

Ch 1 Output

output

The digital output of the Channel 1 SPM detector when enabled. The

format of the signal at this pin, in common with Ch 2, is selectable to

either 'Tone Follower' or 'Packet' mode via the Output Select input.

8

power

9

Ch 1 Amp Out

output

The output of the Channel 1 Input Amplifier. See Figure 2 and Figure 8.

10

Ch 1 Amp In (-):

input

The negative input to the Channel 1 Input Amplifier. See Figure 2 and

Figure 8.

11

Ch 1 Amp In

(+):

input

The positive input to the Channel 1 Input Amplifier. See Figure 2 and

Figure 8.

12

power

Negative supply (GND).

13

N/C

No internal connection; leave open circuit.

14

Ch 2 Amp In

(+):

input

The positive input to the Channel 2 Input Amplifier. See Figure 2 and

Figure 8.

15

Ch 2 Amp In (-):

input

The negative input to the Channel 2 Input Amplifier. See Figure 2 and

Figure 8.

16

Ch 2 Amp Out

output

The output of the Channel 2 Input Amplifier. See Figure 2 and Figure 8.

17

Output Select

input

A logic input to set the Channel 1 and Channel 2 output modes. When

high (logic '1'), the outputs are in the Tone Follower mode; when low

(logic '0'), the outputs are in the Packet mode.

18

Preset Level

input

A logic input to set the sensitivity mode of the MX641. When high (logic

'1'), both channels are in the Fixed Sensitivity mode. The external

components govern the input sensitivity; the System Select input

selects 12kHz or 16kHz operation. When low (logic '0'), both channels

are in the Controlled Sensitivity mode. Device sensitivities and system

selection are via the Chip Select/Serial Data/Serial Clock inputs. This

input has an internal pull-up resistor on chip (Fixed Sensitivity Mode).