CBTL06DP211

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© NXP B.V. 2011. All rights reserved.

Product data sheet

Rev. 1 — 21 February 2011

5 of 18

NXP Semiconductors

CBTL06DP211

DisplayPort Gen1 2 : 1 multiplexer

6.2 Pin description

Table 2.

Pin description

Symbol

Ball

Type

Description

GPU_SEL

A1

3.3 V low-voltage CMOS

single-ended input

Selects between two multiplexer/switch paths. When HIGH, path 2

left-side is connected to its corresponding right-side I/O. When

LOW, path 1 left-side is connected to its corresponding right-side

I/O.

DDC_AUX_SEL

C2

3.3 V low-voltage CMOS

single-ended input

Selects between DDC and AUX paths. When HIGH, the

DDC_CLKn and DDC_DATn I/Os are connected to their respective

AUX terminals. When LOW, the AUX+ and AUX

− I/Os are

connected to their respective AUX terminals.

XSD

B7

3.3 V low-voltage CMOS

single-ended input

Shutdown pin. Should be driven HIGH or connected to VDD for

normal operation. When LOW, all paths are switched off

(non-conducting) and supply current consumption is minimized.

TST0

G2

3.3 V low-voltage CMOS

single-ended input

Test pin for NXP use only. Should be tied to ground in normal

operation.

IN1_0+

B4

differential I/O

Four high-speed differential pairs for DisplayPort or PCI Express

signals, path 1, left-side.

IN1_0

−

A4

differential I/O

IN1_1+

B5

differential I/O

IN1_1

−

A5

differential I/O

IN1_2+

B6

differential I/O

IN1_2

−

A6

differential I/O

IN1_3+

A8

differential I/O

IN1_3

−

A9

differential I/O

IN2_0+

B8

differential I/O

Four high-speed differential pairs for DisplayPort or PCI Express

signals, path 2, left-side.

IN2_0

−

B9

differential I/O

IN2_1+

D8

differential I/O

IN2_1

−

D9

differential I/O

IN2_2+

E8

differential I/O

IN2_2

−

E9

differential I/O

IN2_3+

F8

differential I/O

IN2_3

−

F9

differential I/O

OUT_0+

B2

differential I/O

Four high-speed differential pairs for DisplayPort or PCI Express

signals, right-side.

OUT_0

−

B1

differential I/O

OUT_1+

D2

differential I/O

OUT_1

−

D1

differential I/O

OUT_2+

E2

differential I/O

OUT_2

−

E1

differential I/O

OUT_3+

F2

differential I/O

OUT_3

−

F1

differential I/O

AUX1+

H9

differential I/O

High-speed differential pair for AUX signals, path 1, left-side.

AUX1

−

J9

differential I/O

AUX2+

H6

differential I/O

High-speed differential pair for AUX signals, path 2, left-side.

AUX2

−

J6

differential I/O