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PCF8532 Datasheet(PDF) 23 Page - NXP Semiconductors

Part # PCF8532
Description  Universal LCD driver for low multiplex rates
PDF  49 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

PCF8532 Datasheet(HTML) 23 Page - NXP Semiconductors

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PCF8532
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 10 February 2011
23 of 49
NXP Semiconductors
PCF8532
Universal LCD driver for low multiplex rates
7.16.5 I2C-bus controller
The PCF8532 acts as an I2C-bus slave receiver. It does not initiate I2C-bus transfers or
transmit data to an I2C-bus master receiver. The only data output from the PCF8532 are
the acknowledge signals of the selected devices. Device selection depends on the
I2C-bus slave address, on the transferred command data and on the hardware
subaddress.
In single device application, the hardware subaddress inputs A0 and A1 are normally tied
to VSS which defines the hardware subaddress 0. In multiple device applications A0
and A1 are tied to VSS or VDD in accordance with a binary coding scheme such that no
two devices with a common I2C-bus slave address have the same hardware subaddress.
7.16.6 Input filters
To enhance noise immunity in electrically adverse environments, RC low-pass filters are
provided on the SDA and SCL lines.
7.16.7 I2C-bus protocol
Two I2C-bus slave addresses (0111 000 and 0111 001) are reserved for the PCF8532.
The least significant bit of the slave address that a PCF8532 responds to is defined by the
level tied at its input SA0. The PCF8532 is a write only device and does not respond to a
read access. Two types of PCF8532 can be distinguished on the same I2C-bus which
allows:
• Up to 8 PCF8532 on the same I2C-bus for very large LCD applications
• The use of two types of LCD multiplex on the same I2C-bus.
The I2C-bus protocol is shown in Figure 17. The sequence is initiated with a START
condition (S) from the I2C-bus master which is followed by one of the two PCF8532 slave
addresses available. All PCF8532 with the corresponding SA0 level acknowledge in
parallel to the slave address, but all PCF8532 with the alternative SA0 level ignore the
whole I2C-bus transfer.
Fig 16. Acknowledgement on the I2C-bus
mbc602
S
START
condition
9
8
2
1
clock pulse for
acknowledgement
not acknowledge
acknowledge
data output
by transmitter
data output
by receiver
SCL from
master



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