R5F2LA36ADFP datasheet(29/106 Pages) RENESAS

29 / 106 page

R8C/LA3A Group, R8C/LA5A Group, R8C/LA6A Group, R8C/LA8A Group

2. Central Processing Unit (CPU)

R01DS0011EJ0100 Rev.1.00

Page 29 of 102

Dec 21, 2010

Central Processing Unit (CPU)

Figure 2.1 shows the CPU Registers. The CPU contains 13 registers. R0, R1, R2, R3, A0, A1, and FB configure a

Figure 2.1

CPU Registers

b31

b15

b8b7

Data registers (1)

Address registers (1)

R0H (high-order of R0)

INTBH

b15

b19

INTBL

Frame base register (1)

The 4 high-order bits of INTB are INTBH and

the 16 low-order bits of INTB are INTBL.

Interrupt table register

b19

USP

Program counter

ISP

User stack pointer

Interrupt stack pointer

Static base register

FLG

Flag register

Carry flag

Debug flag

Zero flag

Sign flag

Overflow flag

Interrupt enable flag

Stack pointer select flag

Reserved bit

Processor interrupt priority level

Reserved bit

IPL

b15

Note:

1. These registers configure a register bank.

There are two sets of register banks.

R1H (high-order of R1)

R0L (low-order of R0)

R1L (low-order of R1)

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