Analog Integrated Circuit Device Data

Freescale Semiconductor

11

33874

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

POWER OUTPUT TIMING (HS0, HS1, HS2, HS3) (continued)

Over-current High Detection Blanking Time

1.0

5.0

20

μs

CS

to CSNS Valid Time(24)

–

–

10

μs

Watchdog Timeout(25)

WD[1:0] : 00

WD[1:0] : 01

WD[1:0] : 10

WD[1:0] : 11

446

223

1800

900

558

279

2250

1125

725

363

2925

1463

ms

Direct Input Switching Frequency (DICR D3 = 0)

-

300

-

Hz

SPI INTERFACE CHARACTERISTICS (RST, CS, SCLK, SI, SO)

Maximum Frequency of SPI Operation

–

–

3.0

MHz

Required Low-state Duration for RST(26)

–

50

350

ns

Rising Edge of CS to Falling Edge of CS (Required Setup Time)(27)

–

–

300

ns

Rising Edge of RST to Falling Edge of CS (Required Setup Time)(27)

–

–

5.0

μs

Falling Edge of CS to Rising Edge of SCLK (Required Setup Time)(27)

–

50

167

ns

Required High-state Duration of SCLK (Required Setup Time)(27)

–

–

167

ns

Required Low-state Duration of SCLK (Required Setup Time)(27)

–

–

167

ns

Falling Edge of SCLK to Rising Edge of CS (Required Setup Time)(27)

–

50

167

ns

SI to Falling Edge of SCLK (Required Setup Time)(28)

–

25

83

ns

Falling Edge of SCLK to SI (Required Setup Time)(28)

–

25

83

ns

SO Rise Time

–

25

50

ns

SO Fall Time

–

25

50

ns

SI, CS, SCLK, Incoming Signal Rise Time(28)

–

–

50

ns

SI, CS, SCLK, Incoming Signal Fall Time(28)

–

–

50

ns

Time from Falling Edge of CS to SO Low-impedance(29)

–

–

145

ns

Time from Rising Edge of CS to SO High-impedance(30)

–

65

145

ns

Time from Rising Edge of SCLK to SO Data Valid(31)

–

65

105

ns

Notes

24.

Time necessary for the CSNS to be with ±5% of the targeted value.

25.

Watchdog timeout delay measured from the rising edge of WAKE or RST from a sleep state condition, to output turn-ON with the output

watchdog timeouts.

26.

RST

low duration measured with outputs enabled and going to OFF or disabled condition.

27.

Maximum setup time required for the 33874 is the minimum guaranteed time needed from the microcontroller.

28.

Rise and Fall time of incoming SI, CS, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

29.

Time required for output status data to be available for use at SO. 1.0k

Ω on pull-up on CS.

30.

Time required for output status data to be terminated at SO. 1.0k

Ω on pull-up on CS.

31.

Time required to obtain valid data out from SO following the rise of SCLK.

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0V

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit