SIZE

CODE IDENT NO.

UNSPECIFIED TOLERANCES

DWG NO.

REV.

SHEET

A

00136

N/A

DOC200103

C

9

7.2

Optional Design, Test and Data Parameters. Test and documentation requirements above that

of the standard high reliability model shall be specified by separate purchase order line items

(as listed in ¶ 5.2c thru k).

1/. All unassigned pins have no internal connections or ties.

TABLE 1 - Item Identification and Package Outline

PIN I/O 1/

HI-REL

STANDARD

MODEL #

PACKAGE

OUTPUT

Vcc

Out

Gnd/Case

EFC

MECHANIC

AL

OUTLINE

2101

24 Pin DDIP

CMOS

24

13

12

1

FIGURE 1

2102

32 Lead Flatpack

CMOS

11, 13

12

5

4

FIGURE 2

2103

24 Lead Flatpack

CMOS

24

13

12

1

FIGURE 3

2104

14 Lead Flatpack

CMOS

2

13

1, 3, 7, 12, 14

6

FIGURE 4

2111

24 Pin DDIP

Sine

24

13

12

1

FIGURE 1

2112

32 Lead Flatpack

Sine

11, 13

12

5

4

FIGURE 2

2113

24 Lead Flatpack

Sine

24

13

12

1

FIGURE 3

2114

14 Lead Flatpack

Sine

2

13

7, 14

6

FIGURE 4