SIZE

CODE IDENT NO.

UNSPECIFIED TOLERANCES

DWG NO.

REV.

SHEET

A

00136

N/A

DOC200103

C

19

SEMICONDUCTOR ENHANCED ELEMENT EVALUATION

Subgroup

Class

Test

Mil-STD-750

Quantity

Mil-PRF-

38534

Reference

K

Method

Condition

(accept number)

Paragraph

1

X

Element Electrical

A. May perform at wafer level

B. All failures shall be removed

from the lot

Perform at room

ambient

100%

C.3.3.1

2

X

Element Visual

2069, 2070,

2072, 2073

100%

C.3.3.2

3

X

Internal Visual

2069, 2070,

2072, 2073, 2074

10(0) or 22(0)

(Notes 1 & 2)

C.3.3.3

C.3.3.4.2

4

X

Temperature Cycling

1051

C

C.3.3.3

X

Surge Current

(when applicable)

4066

A or B as

specified

X

Constant Acceleration

2006

2001

Y1 direction

20,000 G /

10,000 G for

Pd ≥ 10W

10(0)

22(0)

(See Notes 1 & 2)

X

Interim Electrical

C.3.3.4.3

X

High Temperature

Reverse Bias (HTRB)

1039

1042

1038

A

B

A

X

Interim Electrical & Delta

Complete

Within 16 hrs of

HTRB

completion

X

Burn-In 240 hours

1039, 1042

1038

1040

B

A

B

X

Post Burn-In Electrical

C.3.3.4.3

X

Steady State Life

1000 hours

1026

1037

1042

1048

X

Final Electrical

C.3.3.4.3

5

X

Wire Bond Evaluation

2011

10(0) wires or

20(1) wires

C.3.3.3

C.3.3.5

6

X

SEM

2018

2077

See method 2018

or 2077 & Note 2

C.3.3.6

NOTES:

1. Subgroups 3, 4, & 5 shall be performed on a sample of 10 die if the wafer lot is from a QPL/QML line. If the die are from

commercial wafer lots, then the sample size shall be 22 die. Die from QPL/QML wafers not meeting the QPL/QML

requirements and downgraded to commercial grade shall not be used.

2. Subgroups 3, 4 & 5 shall be performed in the order listed in Table 1. Subgroup 6 may be performed at any time.