Pad No.

X

Y

Pad No.

X

Y

Pad No.

X

Y

14

-1779.30

-149.00

47

1522.60

-1712.30

80

823.50

1708.30

15

-1779.30

-277.00

48

1654.40

-1712.30

81

691.70

1708.30

16

-1779.30

-408.80

49

1782.40

-1712.30

82

563.70

1708.30

17

-1779.30

-536.80

50

1775.70

-1411.10

83

431.90

1708.30

18

-1779.30

-668.60

51

1775.70

-1283.10

84

303.90

1708.30

19

-1779.30

-796.60

52

1775.70

-1151.30

85

172.10

1708.30

20

-1779.30

-928.80

53

1775.70

-1023.30

86

44.10

1708.30

21

-1779.30

-1056.80

54

1775.70

-891.50

87

-87.70

1708.30

22

-1779.30

-1189.00

55

1775.70

-763.50

88

-215.70

1708.30

23

-1690.00

-1375.40

56

1775.70

-631.70

89

-347.50

1708.30

24

-1690.00

-1515.40

57

1775.70

-503.70

90

-475.50

1708.30

25

-1690.00

-1651.00

58

1775.70

-371.90

91

-607.30

1708.30

26

-1430.20

-1599.90

59

1775.70

-243.90

92

-735.30

1708.30

27

-1294.80

-1599.90

60

1775.70

-112.10

93

-867.10

1708.30

28

-1149.50

-1599.90

61

1775.70

15.90

94

-995.10

1708.30

29

-1013.90

-1599.90

62

1775.70

147.70

95

-1126.90

1708.30

30

-872.80

-1600.00

63

1775.70

275.70

96

-1254.90

1708.30

31

-738.30

-1600.00

64

1775.70

407.50

97

-1386.70

1708.30

32

-600.10

-1600.00

65

1775.70

535.50

98

-1514.70

1708.30

33

-465.60

-1600.00

66

1775.70

667.30

99

-1646.50

1708.30

Pad Description

Pad No.

Pad Name

I/O

Description

23

CS

I

Chip selection input with pull-high resistor. When the CS is logic high, the

data and command read from or write to the HT1647 are disabled. The serial

interface circuit is also reset. But if the CS is at a logic low level and is input to

the CS pad, the data and command transmission between the host control-

ler and the HT1647 are all enabled.

24

RD

I

READ clock input with pull-high resistor. Data in the RAM of the HT1647 are

clocked out on the rising edge of the RD signal. The clocked out data will ap-

pear on the data line. The host controller can use the next falling edge to

latch the clocked out data.

25

WR

I

WRITE clock input with pull-high resistor. Data on the DATA line are latched

into the HT1647 on the rising edge of the WR signal.

26~29

DB0~DB3

I/O

Parallel data input/output with a pull-high resistor

30

VSS

¾

Negative power supply for logic circuit, ground

31

OSCI

I

The OSCI and OSCO pads are connected to a 32.768kHz crystal in order to

generate a system clock. If the system clock comes from an external clock

source, the external clock source should be connected to the OSCI pad. But

if an on-chip RC oscillator is selected, the OSCI and OSCO pads can be left

open.

32

OSCO

O

33

VDD

¾

Positive power supply for logic circuit

34

VLCD

I

Power supply for LCD driver circuit

35

IRQ

O

Time base or Watchdog Timer overflow flag, NMOS open drain output.

36, 37

BZ, BZ

O

2kHz or 4kHz frequency output pair (tristate output buffer)

38~41

T1~T4

I

Not connected

42~57

COM0~COM15

O

LCD common outputs

58~99,

1~22

SEG0~SEG63

O

LCD segment outputs

HT1647

Rev. 1.40

4

November 9, 2010

PATENTED