R5F2136CMDFD datasheet(48/61 Pages) RENESAS

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R8C/36M Group

5. Electrical Characteristics

Under development Preliminary document

Specifications in this document are tentative and subject to change.

R01DS0086EJ0010 Rev.0.10

Page 48 of 58

Mar 09, 2011

i = 0 to 2

Figure 5.11

Serial Interface Timing Diagram when VCC = 5 V

Notes:

1. When selecting the digital filter by the INTi input filter select bit, use an INTi input HIGH width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

2. When selecting the digital filter by the INTi input filter select bit, use an INTi input LOW width of either (1/digital filter clock

frequency × 3) or the minimum value of standard, whichever is greater.

Figure 5.12

Input Timing Diagram for External Interrupt INTi and Key Input Interrupt KIi

when VCC = 5 V

Table 5.23

Serial Interface

Symbol

Parameter

Standard

Unit

Min.

Max.

tc(CK)

CLKi input cycle time

When external clock is selected

200

−

tW(CKH)

CLKi input “H” width

100

−

tW(CKL)

CLKi input “L” width

100

−

td(C-Q)

TXDi output delay time

−

th(C-Q)

TXDi hold time

−

tsu(D-C)

RXDi input setup time

−

th(C-D)

RXDi input hold time

−

td(C-Q)

TXDi output delay time

When internal clock is selected

−

tsu(D-C)

RXDi input setup time

−

th(C-D)

RXDi input hold time

−

Table 5.24

External Interrupt INTi (i = 0 to 4) Input, Key Input Interrupt KIi (i = 0 to 3)

Symbol

Parameter

Standard

Unit

Min.

Max.

tW(INH)

INTi input “H” width, KIi input “H” width

250 (1)

—ns

tW(INL)

INTi input “L” width, KIi input “L” width

250 (2)

—ns

tW(CKH)

tC(CK)

tW(CKL)

th(C-Q)

th(C-D)

tsu(D-C)

td(C-Q)

CLKi

TXDi

RXDi

i = 0 to 2

VCC = 5 V

INTi input

(i = 0 to 4)

tW(INL)

tW(INH)

VCC = 5 V

KIi input

(i = 0 to 3)

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