MPC5675K datasheet(111/140 Pages) FREESCALE

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Electrical characteristics

MPC5675K Microcontroller Data Sheet, Rev. 4

Preliminary—Subject to Change Without Notice

Freescale Semiconductor

111

Figure 31 shows the DDR SDRAM write timing.

Figure 31. DDR write timing

Figure 32 and Figure 33 show the DDR SDRAM read timing.

Figure 32. DDR read timing, DQ vs. DQS

tDQSQ

CC DQS-DQ skew for DQS and associated DQ inputs2 –(tCK/4 – 600) (tCK/4–600) ps

tDQSEN

CC DQS window start position related to CAS read

command1, 2, 3, 4, 5

TBD

NOTES:

1 Measured with clock pin loaded with differential 100 ohm termination resistor.

2 All transitions measured at mid-supply (V

DD_MEM_IO/2).

3 Measured with all outputs except the clock loaded with 50 ohm termination resistor to V

DD_MEM_IO/2.

4 In this window, the first rising edge of DQS should occur. From the start of the window to DQS rising edge, DQS

should be low.

5 Window position is given for t

DQSEN = 2.0 tCK. For other values of tDQSEN, window position is shifted accordingly.

Table 61. DDR and DDR2 (DDR2-400) SDRAM timing specifications (continued)

At recommended operating conditions with VDD_MEM_IO of 5%

No.

Symbol

Parameter

Min

Max

Unit

MCK

tCH

tCL

DQS

tDQSS

DQ, DM (out)

tDS

tDH

tCK

DQS (in)

Any DQ (in)

tDQSQ

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