MPC5675K datasheet(112/140 Pages) FREESCALE

112 / 140 page

MPC5675K Microcontroller Data Sheet, Rev. 4

Preliminary—Subject to Change Without Notice

Electrical characteristics

Freescale Semiconductor

112

Figure 33. DDR read timing, DQSEN

Figure 34 provides the AC test load for the DDR bus.

Figure 34. DDR AC test load

3.22.2

IEEE 1149.1 (JTAG) interface timing

Table 62. JTAG pin AC electrical characteristics

No.

Symbol

Parameter

Conditions

Min Max Unit

1tJCYC

TCK cycle time 1

—100

—

2tJDC

TCK clock pulse width (measured at VDDE/2)

—

3tTCKRISE

TCK rise and fall times (40%–70%)

—

4tTMSS, tTDIS D TMS, TDI data setup time

—

5tTMSH, tTDIH D TMS, TDI data hold time

—

6tTDOV

TCK low to TDO data valid

—

7tTDOI

TCK low to TDO data invalid

—

8tTDOHZ

TCK low to TDO high impedance

—

tBSDV

TCK falling edge to output valid

—

tBSDVZ

TCK falling edge to output valid out of high impedance

—

tBSDHZ

TCK falling edge to output high impedance

—

tBSDST

Boundary scan input valid to TCK rising edge

—

tBSDHT

TCK rising edge to boundary scan input invalid

—

MCK

DQS (in)

tOS

tOH

Command

Address

Read

tDQSEN (min)

tDQSEN

Output

Z0 =50 

RL = 50 

VDD_MEM_IO/2

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